| Message ID | 20211210164741.881161-2-thierry.reding@gmail.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | memory: tegra: Add Tegra234 support | expand |
On 10/12/2021 17:47, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > The #interconnect-cells properties are required to hook up memory > clients to the MC/EMC in interconnects properties. Add a description for > these properties. > > Also, allow multiple reg and interrupt entries required by Tegra194 and > later. I think number of interrupts is fixed and you do not change them for newer SoC, so the message is a little bit not precise. Also the subject does not it the patch - maybe something like - "adjust properties for Tegra196"? > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > Changes in v2: > - drop incomplete BPMP snippet from example > - explicitly set minItems for reg property > - describe MC and EMC general interrupts > > .../nvidia,tegra186-mc.yaml | 78 ++++++++++++++++--- > 1 file changed, 67 insertions(+), 11 deletions(-) > Best regards, Krzysztof
On Sun, Dec 12, 2021 at 07:50:25PM +0100, Krzysztof Kozlowski wrote: > On 10/12/2021 17:47, Thierry Reding wrote: > > From: Thierry Reding <treding@nvidia.com> > > > > The #interconnect-cells properties are required to hook up memory > > clients to the MC/EMC in interconnects properties. Add a description for > > these properties. > > > > Also, allow multiple reg and interrupt entries required by Tegra194 and > > later. > > I think number of interrupts is fixed and you do not change them for > newer SoC, so the message is a little bit not precise. Also the subject > does not it the patch - maybe something like - "adjust properties for > Tegra196"? Yeah, I forgot to update the commit message after making the changes in v2. I'll send out v3 with an updated commit message. Thanks, Thierry
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 611bda38d187..b496564b1bdf 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -33,10 +33,12 @@ properties: - nvidia,tegra194-mc reg: - maxItems: 1 + minItems: 1 + maxItems: 3 interrupts: - maxItems: 1 + items: + - description: MC general interrupt "#address-cells": const: 2 @@ -48,6 +50,9 @@ properties: dma-ranges: true + "#interconnect-cells": + const: 1 + patternProperties: "^external-memory-controller@[0-9a-f]+$": description: @@ -65,10 +70,12 @@ patternProperties: - nvidia,tegra194-emc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: - maxItems: 1 + items: + - description: EMC general interrupt clocks: items: @@ -78,11 +85,65 @@ patternProperties: items: - const: emc + "#interconnect-cells": + const: 0 + nvidia,bpmp: $ref: /schemas/types.yaml#/definitions/phandle description: phandle of the node representing the BPMP + allOf: + - if: + properties: + compatible: + const: nvidia,tegra186-emc + then: + properties: + reg: + maxItems: 1 + + - if: + properties: + compatible: + const: nvidia,tegra194-emc + then: + properties: + reg: + minItems: 2 + + additionalProperties: false + + required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#interconnect-cells" + - nvidia,bpmp + +allOf: + - if: + properties: + compatible: + const: nvidia,tegra186-mc + then: + properties: + reg: + maxItems: 1 + + - if: + properties: + compatible: + const: nvidia,tegra194-mc + then: + properties: + reg: + minItems: 3 + +additionalProperties: false + required: - compatible - reg @@ -90,8 +151,6 @@ required: - "#address-cells" - "#size-cells" -additionalProperties: false - examples: - | #include <dt-bindings/clock/tegra186-clock.h> @@ -124,12 +183,9 @@ examples: clocks = <&bpmp TEGRA186_CLK_EMC>; clock-names = "emc"; + #interconnect-cells = <0>; + nvidia,bpmp = <&bpmp>; }; }; }; - - bpmp: bpmp { - compatible = "nvidia,tegra186-bpmp"; - #clock-cells = <1>; - };