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Fri, 19 Nov 2021 07:27:36 +0000 Received: from Asurada-Nvidia.nvidia.com (172.20.187.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 19 Nov 2021 07:27:36 +0000 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , Subject: [PATCH v3 3/5] iommu/arm-smmu-v3: Pass cmdq pointer in arm_smmu_cmdq_issue_cmdlist() Date: Thu, 18 Nov 2021 23:19:57 -0800 Message-ID: <20211119071959.16706-4-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211119071959.16706-1-nicolinc@nvidia.com> References: <20211119071959.16706-1-nicolinc@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5de930be-b995-436c-5edc-08d9ab2e0fcc X-MS-TrafficTypeDiagnostic: BL0PR12MB4675: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QfP51KMxUm23Yz7qg4t8XDnDaWkwTSFm1vY7JQu3Nq4IcB7P3+mLuCGvM4/q+zNm5Ess3sWes+aPw2ctv5QoK1ProX6PZAa4N4LkrifgWYq3oj/xhUlHmuwHqrAeOrrAYhZ5md5X1IHOTX6CIFD4nynYtu338Lcj+mEwPZOKO44XbysLk/+ZUGfpnme1AtPP6ShcYU0O2EeIpoKBmUe14+8rXjRix/GRG4WDIxSRv+8A0/HYfiX6AWE/gW084Wt7jXhwkOmVP+UPmoUUC6XBAfi5v+wjthZDJs9GUqVwFCkJrgMWbZZqi7zbSobf3+ZPlbk7iotjicElkwrOoL83OFU6cXVMV7v/HScTb/o9e/pJULEL351sO3WBCJwKsPER2r7pPHgA1Yd1L8dqdbe0BhZPmzlqH6NQ75X4XmOwBS+6BY7jMeN61MhN6butpjIqyCIAcJ++coAPQApbnc4IbGKDZ/c3demZGIltLHrNvYpRMRiwmUGAM+dDACoIR+PmtGENp6oj4zon5A3derjiDsFZOmgmmEi44fS1qIyp2k9UM3uUlV/1SToF7oU83tKF+epb8EvaAkiFT/Nwekw5jUUb6sZE/cJrz18k6HSCX8ukIWuKyjYiAsdkoLZZtjif033CvEazF9hWdEoLntON3yzyc9rSjUwoikp0/oFI4gvpLJz4393ScdRO9P+HJmuJB7pNs1sC8e3MRolqrVPpuw== X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(6666004)(54906003)(7636003)(7416002)(4326008)(8936002)(36906005)(70586007)(26005)(5660300002)(508600001)(316002)(356005)(82310400003)(8676002)(110136005)(70206006)(7696005)(426003)(2906002)(83380400001)(107886003)(36860700001)(1076003)(336012)(47076005)(86362001)(36756003)(2616005)(186003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2021 07:27:37.0503 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5de930be-b995-436c-5edc-08d9ab2e0fcc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4675 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The driver currently calls arm_smmu_get_cmdq() helper internally in different places, though they are all actually called from the same source -- arm_smmu_cmdq_issue_cmdlist() function. This patch changes this to pass the cmdq pointer to these functions instead of calling arm_smmu_get_cmdq() every time. This also helps CMDQV extension in NVIDIA Grace SoC, whose driver'd maintain its own cmdq pointers and needs to redirect arm_smmu->cmdq to that upon seeing a supported command by checking its opcode. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 6be20e926f63..188865ec9a33 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -586,11 +586,11 @@ static void arm_smmu_cmdq_poll_valid_map(struct arm_smmu_cmdq *cmdq, /* Wait for the command queue to become non-full */ static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { unsigned long flags; struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); int ret = 0; /* @@ -621,11 +621,11 @@ static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, * Must be called with the cmdq lock held in some capacity. */ static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { int ret = 0; struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); u32 *cmd = (u32 *)(Q_ENT(&cmdq->q, llq->prod)); queue_poll_init(smmu, &qp); @@ -645,10 +645,10 @@ static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, * Must be called with the cmdq lock held in some capacity. */ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); u32 prod = llq->prod; int ret = 0; @@ -695,12 +695,13 @@ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, } static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { if (smmu->options & ARM_SMMU_OPT_MSIPOLL) - return __arm_smmu_cmdq_poll_until_msi(smmu, llq); + return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); - return __arm_smmu_cmdq_poll_until_consumed(smmu, llq); + return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); } static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, u64 *cmds, @@ -757,7 +758,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, while (!queue_has_space(&llq, n + sync)) { local_irq_restore(flags); - if (arm_smmu_cmdq_poll_until_not_full(smmu, &llq)) + if (arm_smmu_cmdq_poll_until_not_full(smmu, cmdq, &llq)) dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); local_irq_save(flags); } @@ -833,7 +834,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, /* 5. If we are inserting a CMD_SYNC, we must wait for it to complete */ if (sync) { llq.prod = queue_inc_prod_n(&llq, n); - ret = arm_smmu_cmdq_poll_until_sync(smmu, &llq); + ret = arm_smmu_cmdq_poll_until_sync(smmu, cmdq, &llq); if (ret) { dev_err_ratelimited(smmu->dev, "CMD_SYNC timeout at 0x%08x [hwprod 0x%08x, hwcons 0x%08x]\n",