Message ID | 20211118074101.165168-1-deng.changcheng@zte.com.cn |
---|---|
State | Not Applicable |
Headers | show |
Series | [v2] clk: tegra: Use div64_ul instead of do_div | expand |
diff --git a/drivers/clk/tegra/clk-utils.c b/drivers/clk/tegra/clk-utils.c index 1a5daae4e501..12658add9dd7 100644 --- a/drivers/clk/tegra/clk-utils.c +++ b/drivers/clk/tegra/clk-utils.c @@ -26,7 +26,7 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width, if (flags & TEGRA_DIVIDER_ROUND_UP) divider_ux1 += rate - 1; - do_div(divider_ux1, rate); + divider_ux1 = div64_ul(divider_ux1, rate); if (flags & TEGRA_DIVIDER_INT) divider_ux1 *= mul;