| Message ID | 20210510231737.30313-7-digetx@gmail.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | Couple improvements for Tegra clk driver | expand |
On Tue, May 11, 2021 at 02:17:35AM +0300, Dmitry Osipenko wrote: > Check whether thermal DIV2 throttle is active in order to report > the CPU frequency properly. This very useful for userspace tools > like cpufreq-info which show actual frequency asserted from hardware. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++++++++++++++-- > drivers/clk/tegra/clk-tegra30.c | 2 +- > 2 files changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c > index a03119c30456..f75822b71d0e 100644 > --- a/drivers/clk/tegra/clk-tegra-super-cclk.c > +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c > @@ -25,6 +25,8 @@ > > #define SUPER_CDIV_ENB BIT(31) > > +#define TSENSOR_SLOWDOWN BIT(23) > + > static struct tegra_clk_super_mux *cclk_super; > static bool cclk_on_pllx; > > @@ -47,10 +49,20 @@ static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, > static unsigned long cclk_super_recalc_rate(struct clk_hw *hw, > unsigned long parent_rate) > { > + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); > + u32 val = readl_relaxed(super->reg); > + unsigned int div2; > + > + /* check whether thermal throttling is active */ > + if (val & TSENSOR_SLOWDOWN) > + div2 = 2; > + else > + div2 = 1; > + > if (cclk_super_get_parent(hw) == PLLX_INDEX) > - return parent_rate; > + return parent_rate / div2; > > - return tegra_clk_super_ops.recalc_rate(hw, parent_rate); > + return tegra_clk_super_ops.recalc_rate(hw, parent_rate) / div2; > } Could you check if the compiler can optimize out the division? I know this is a slow path, but nevertheless the 'shr' version would be the same amount of source code. Best Regrads Michał Mirosław
11.05.2021 17:41, Michał Mirosław пишет: > On Tue, May 11, 2021 at 02:17:35AM +0300, Dmitry Osipenko wrote: >> Check whether thermal DIV2 throttle is active in order to report >> the CPU frequency properly. This very useful for userspace tools >> like cpufreq-info which show actual frequency asserted from hardware. >> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> >> --- >> drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++++++++++++++-- >> drivers/clk/tegra/clk-tegra30.c | 2 +- >> 2 files changed, 15 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c >> index a03119c30456..f75822b71d0e 100644 >> --- a/drivers/clk/tegra/clk-tegra-super-cclk.c >> +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c >> @@ -25,6 +25,8 @@ >> >> #define SUPER_CDIV_ENB BIT(31) >> >> +#define TSENSOR_SLOWDOWN BIT(23) >> + >> static struct tegra_clk_super_mux *cclk_super; >> static bool cclk_on_pllx; >> >> @@ -47,10 +49,20 @@ static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, >> static unsigned long cclk_super_recalc_rate(struct clk_hw *hw, >> unsigned long parent_rate) >> { >> + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); >> + u32 val = readl_relaxed(super->reg); >> + unsigned int div2; >> + >> + /* check whether thermal throttling is active */ >> + if (val & TSENSOR_SLOWDOWN) >> + div2 = 2; >> + else >> + div2 = 1; >> + >> if (cclk_super_get_parent(hw) == PLLX_INDEX) >> - return parent_rate; >> + return parent_rate / div2; >> >> - return tegra_clk_super_ops.recalc_rate(hw, parent_rate); >> + return tegra_clk_super_ops.recalc_rate(hw, parent_rate) / div2; >> } > > Could you check if the compiler can optimize out the division? I know this > is a slow path, but nevertheless the 'shr' version would be the same amount > of source code. Hello Michał, GCC can't optimize that division. I'll wait for more comments and then update this patch in v8 with yours suggestion. Thank you for taking a look at the patches.
diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c index a03119c30456..f75822b71d0e 100644 --- a/drivers/clk/tegra/clk-tegra-super-cclk.c +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -25,6 +25,8 @@ #define SUPER_CDIV_ENB BIT(31) +#define TSENSOR_SLOWDOWN BIT(23) + static struct tegra_clk_super_mux *cclk_super; static bool cclk_on_pllx; @@ -47,10 +49,20 @@ static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, static unsigned long cclk_super_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); + u32 val = readl_relaxed(super->reg); + unsigned int div2; + + /* check whether thermal throttling is active */ + if (val & TSENSOR_SLOWDOWN) + div2 = 2; + else + div2 = 1; + if (cclk_super_get_parent(hw) == PLLX_INDEX) - return parent_rate; + return parent_rate / div2; - return tegra_clk_super_ops.recalc_rate(hw, parent_rate); + return tegra_clk_super_ops.recalc_rate(hw, parent_rate) / div2; } static int cclk_super_determine_rate(struct clk_hw *hw, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index a33688b2359e..5b6bd138be84 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -930,7 +930,7 @@ static void __init tegra30_super_clk_init(void) /* CCLKG */ clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents, ARRAY_SIZE(cclk_g_parents), - CLK_SET_RATE_PARENT, + CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, clk_base + CCLKG_BURST_POLICY, 0, NULL); clks[TEGRA30_CLK_CCLK_G] = clk;
Check whether thermal DIV2 throttle is active in order to report the CPU frequency properly. This very useful for userspace tools like cpufreq-info which show actual frequency asserted from hardware. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++++++++++++++-- drivers/clk/tegra/clk-tegra30.c | 2 +- 2 files changed, 15 insertions(+), 3 deletions(-)