| Message ID | 20201104134810.21026-1-digetx@gmail.com |
|---|---|
| State | Deferred |
| Headers | show |
| Series | [v1] clk: tegra30: Use 300MHz for video decoder by default | expand |
Quoting Dmitry Osipenko (2020-11-04 05:48:10) > The 600MHz is a too high clock rate for some SoC versions for the video > decoder hardware and this may cause stability issues. Use 300MHz for the > video decoder by default, which is supported by all hardware versions. > > Fixes: ed1a2459e20c ("clk: tegra: Add Tegra20/30 EMC clock implementation") > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- Should this go to clk-fixes? Thierry?
15.11.2020 00:16, Stephen Boyd пишет: > Quoting Dmitry Osipenko (2020-11-04 05:48:10) >> The 600MHz is a too high clock rate for some SoC versions for the video >> decoder hardware and this may cause stability issues. Use 300MHz for the >> video decoder by default, which is supported by all hardware versions. >> >> Fixes: ed1a2459e20c ("clk: tegra: Add Tegra20/30 EMC clock implementation") >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> >> --- > > Should this go to clk-fixes? Thierry? > Either way should be good. The fix isn't critical because 600MHz seems to be working okay on unsupported hardware. Potentially this could vary depending on a board, but then I don't think that there are actively-supported boards which would notice this change. Likely that this patch will be backported by a bot anyways because of the fixes tag.
Quoting Dmitry Osipenko (2020-11-15 06:10:04) > 15.11.2020 00:16, Stephen Boyd пишет: > > Quoting Dmitry Osipenko (2020-11-04 05:48:10) > >> The 600MHz is a too high clock rate for some SoC versions for the video > >> decoder hardware and this may cause stability issues. Use 300MHz for the > >> video decoder by default, which is supported by all hardware versions. > >> > >> Fixes: ed1a2459e20c ("clk: tegra: Add Tegra20/30 EMC clock implementation") > >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > >> --- > > > > Should this go to clk-fixes? Thierry? > > > > Either way should be good. The fix isn't critical because 600MHz seems > to be working okay on unsupported hardware. > > Potentially this could vary depending on a board, but then I don't think > that there are actively-supported boards which would notice this change. > Ok sounds like Thierry can pick it up.
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 37244a7e68c2..98923c4674bf 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1248,7 +1248,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, - { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 600000000, 0 }, + { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
The 600MHz is a too high clock rate for some SoC versions for the video decoder hardware and this may cause stability issues. Use 300MHz for the video decoder by default, which is supported by all hardware versions. Fixes: ed1a2459e20c ("clk: tegra: Add Tegra20/30 EMC clock implementation") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clk/tegra/clk-tegra30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)