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[v3,04/15] phy: tegra: xusb: tegra210: Do not reset UPHY PLL

Message ID 20200909081041.3190157-5-jckuo@nvidia.com
State New
Headers show
Series Tegra XHCI controller ELPG support | expand

Commit Message

JC Kuo Sept. 9, 2020, 8:10 a.m. UTC
Once UPHY PLL hardware power sequencer is enabled, do not assert
reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken.
This commit removes reset_control_assert(pcie->rst) and
reset_control_assert(sata->rst) from PEX/SATA UPHY disable procedure.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
   new, was a part of "phy: tegra: xusb: Rearrange UPHY init on Tegra210"

 drivers/phy/tegra/xusb-tegra210.c | 2 --
 1 file changed, 2 deletions(-)
diff mbox series


diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
index f06e7bc7a51b..ef4bbcbed60b 100644
--- a/drivers/phy/tegra/xusb-tegra210.c
+++ b/drivers/phy/tegra/xusb-tegra210.c
@@ -504,7 +504,6 @@  static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl)
 	if (--pcie->enable > 0)
 		goto unlock;
-	reset_control_assert(pcie->rst);
@@ -746,7 +745,6 @@  static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl)
 	if (--sata->enable > 0)
 		goto unlock;
-	reset_control_assert(sata->rst);