diff mbox series

[v3,1/2] dt-bindings: Add documentation for GV11B GPU

Message ID 20200717083609.557205-1-thierry.reding@gmail.com
State Accepted
Headers show
Series [v3,1/2] dt-bindings: Add documentation for GV11B GPU | expand

Commit Message

Thierry Reding July 17, 2020, 8:36 a.m. UTC
From: Thierry Reding <treding@nvidia.com>

The GV11B's device tree bindings are the same as for GP10B, though the
GPU is not completely compatible, so all that is needed is a different
compatible string.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- document the "fuse" clock which needs to be enabled during the GPU
  initialization

 .../devicetree/bindings/gpu/nvidia,gk20a.txt  | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

Comments

Jon Hunter July 17, 2020, 8:40 a.m. UTC | #1
On 17/07/2020 09:36, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The GV11B's device tree bindings are the same as for GP10B, though the
> GPU is not completely compatible, so all that is needed is a different
> compatible string.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v3:
> - document the "fuse" clock which needs to be enabled during the GPU
>   initialization
> 
>  .../devicetree/bindings/gpu/nvidia,gk20a.txt  | 25 +++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
> index f32bbba4d3bc..662a3c8a7d29 100644
> --- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
> +++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
> @@ -6,6 +6,7 @@ Required properties:
>    - nvidia,gk20a
>    - nvidia,gm20b
>    - nvidia,gp10b
> +  - nvidia,gv11b
>  - reg: Physical base address and length of the controller's registers.
>    Must contain two entries:
>    - first entry for bar0
> @@ -25,6 +26,9 @@ Required properties:
>  If the compatible string is "nvidia,gm20b", then the following clock
>  is also required:
>    - ref
> +If the compatible string is "nvidia,gv11b", then the following clock is also
> +required:
> +  - fuse
>  - resets: Must contain an entry for each entry in reset-names.
>    See ../reset/reset.txt for details.
>  - reset-names: Must include the following entries:
> @@ -88,3 +92,24 @@ Example for GP10B:
>  		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
>  		iommus = <&smmu TEGRA186_SID_GPU>;
>  	};
> +
> +Example for GV11B:
> +
> +	gpu@17000000 {
> +		compatible = "nvidia,gv11b";
> +		reg = <0x17000000 0x10000000>,
> +		      <0x18000000 0x10000000>;
> +		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "stall", "nonstall";
> +		clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
> +			 <&bpmp TEGRA194_CLK_GPU_PWR>,
> +			 <&bpmp TEGRA194_CLK_FUSE>;
> +		clock-names = "gpu", "pwr", "fuse";
> +		resets = <&bpmp TEGRA194_RESET_GPU>;
> +		reset-names = "gpu";
> +		dma-coherent;
> +
> +		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
> +		iommus = <&smmu TEGRA194_SID_GPU>;
> +	};
> 


Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
index f32bbba4d3bc..662a3c8a7d29 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
@@ -6,6 +6,7 @@  Required properties:
   - nvidia,gk20a
   - nvidia,gm20b
   - nvidia,gp10b
+  - nvidia,gv11b
 - reg: Physical base address and length of the controller's registers.
   Must contain two entries:
   - first entry for bar0
@@ -25,6 +26,9 @@  Required properties:
 If the compatible string is "nvidia,gm20b", then the following clock
 is also required:
   - ref
+If the compatible string is "nvidia,gv11b", then the following clock is also
+required:
+  - fuse
 - resets: Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names: Must include the following entries:
@@ -88,3 +92,24 @@  Example for GP10B:
 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
 		iommus = <&smmu TEGRA186_SID_GPU>;
 	};
+
+Example for GV11B:
+
+	gpu@17000000 {
+		compatible = "nvidia,gv11b";
+		reg = <0x17000000 0x10000000>,
+		      <0x18000000 0x10000000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "stall", "nonstall";
+		clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
+			 <&bpmp TEGRA194_CLK_GPU_PWR>,
+			 <&bpmp TEGRA194_CLK_FUSE>;
+		clock-names = "gpu", "pwr", "fuse";
+		resets = <&bpmp TEGRA194_RESET_GPU>;
+		reset-names = "gpu";
+		dma-coherent;
+
+		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
+		iommus = <&smmu TEGRA194_SID_GPU>;
+	};