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[v3,39/39] ARM: multi_v7_defconfig: Enable interconnect API

Message ID	20200607185530.18113-40-digetx@gmail.com
State	Superseded
Headers	show Return-Path: <linux-tegra-owner@vger.kernel.org> From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi> Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= <a.swigon@samsung.com>, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v3 39/39] ARM: multi_v7_defconfig: Enable interconnect API Date: Sun, 7 Jun 2020 21:55:30 +0300 Message-Id: <20200607185530.18113-40-digetx@gmail.com> In-Reply-To: <20200607185530.18113-1-digetx@gmail.com> References: <20200607185530.18113-1-digetx@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk
Series	Introduce memory interconnect for NVIDIA Tegra SoCs \| expand [v3,00/39] Introduce memory interconnect for NVIDIA Tegra SoCs [v3,01/39] clk: Export clk_hw_reparent() [v3,02/39] clk: tegra: Remove Memory Controller lock [v3,03/39] clk: tegra: Export Tegra20 EMC kernel symbols [v3,04/39] memory: tegra20-emc: Make driver modular [v3,05/39] memory: tegra30-emc: Make driver modular [v3,06/39] memory: tegra124-emc: Make driver modular [v3,07/39] memory: tegra124-emc: Use devm_platform_ioremap_resource [v3,08/39] soc/tegra: fuse: Export tegra_read_ram_code() [v3,09/39] memory: tegra20-emc: Initialize MC timings [v3,10/39] PM / devfreq: tegra20: Silence deferred probe error [v3,11/39] PM / devfreq: tegra30: Silence deferred probe error [v3,12/39] PM / devfreq: tegra20: Use MC timings for building OPP table [v3,13/39] PM / devfreq: tegra30: Use MC timings for building OPP table [v3,14/39] PM / devfreq: tegra20: Add error messages to tegra_devfreq_target() [v3,15/39] PM / devfreq: tegra30: Add error messages to tegra_devfreq_target() [v3,16/39] PM / devfreq: tegra20: Adjust clocks conversion ratio and polling interval [v3,17/39] PM / devfreq: tegra20: Relax Kconfig dependency [v3,18/39] dt-bindings: memory: tegra20: mc: Document new interconnect property [v3,19/39] dt-bindings: memory: tegra20: emc: Document new interconnect property [v3,20/39] dt-bindings: memory: tegra30: mc: Document new interconnect property [v3,21/39] dt-bindings: memory: tegra30: emc: Document new interconnect property [v3,22/39] dt-bindings: host1x: Document new interconnect properties [v3,23/39] dt-bindings: memory: tegra20: Add memory client IDs [v3,24/39] dt-bindings: memory: tegra30: Add memory client IDs [v3,25/39] ARM: tegra: Add interconnect properties to Tegra20 device-tree [v3,26/39] ARM: tegra: Add interconnect properties to Tegra30 device-tree [v3,27/39] interconnect: Relax requirement in of_icc_get_from_provider() [v3,28/39] memory: tegra: Register as interconnect provider [v3,29/39] memory: tegra20-emc: Use devm_platform_ioremap_resource [v3,30/39] memory: tegra20-emc: Continue probing if timings are missing in device-tree [v3,31/39] memory: tegra20-emc: Register as interconnect provider [v3,32/39] memory: tegra20-emc: Create tegra20-devfreq device [v3,33/39] memory: tegra30-emc: Continue probing if timings are missing in device-tree [v3,34/39] memory: tegra30-emc: Register as interconnect provider [v3,35/39] drm/tegra: dc: Support memory bandwidth management [v3,36/39] drm/tegra: dc: Tune up high priority request controls for Tegra20 [v3,37/39] drm/tegra: dc: Extend debug stats with total number of events [v3,38/39] ARM: tegra: Enable interconnect API in tegra_defconfig [v3,39/39] ARM: multi_v7_defconfig: Enable interconnect API

Commit Message

Dmitry Osipenko June 7, 2020, 6:55 p.m. UTC

NVIDIA Tegra now has interconnect providers that are used for memory
bandwidth allocation.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 95543914d3c7..d3b554045dbe 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -1086,6 +1086,7 @@  CONFIG_FSI_MASTER_ASPEED=m
 CONFIG_FSI_SCOM=m
 CONFIG_FSI_SBEFIFO=m
 CONFIG_FSI_OCC=m
+CONFIG_INTERCONNECT=y
 CONFIG_EXT4_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y