From patchwork Sun Jun 7 18:55:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1304853 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=Ctrheq2+; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49g5L428XYz9sRk for ; Mon, 8 Jun 2020 05:00:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728817AbgFGTAG (ORCPT ); Sun, 7 Jun 2020 15:00:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728331AbgFGS5Y (ORCPT ); Sun, 7 Jun 2020 14:57:24 -0400 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 037CCC061A0E; Sun, 7 Jun 2020 11:57:23 -0700 (PDT) Received: by mail-lf1-x141.google.com with SMTP id d7so8855383lfi.12; Sun, 07 Jun 2020 11:57:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z07PPt/u97dYBnTZgvhRJ5rLo7+ZbziTOZ6KMaLiXtU=; b=Ctrheq2+Lk6agPf9hiEOvCmdXzM5uqqaftrWAGWVrhVKMKGMDwZHxP40MhdNi98r79 jRnM/h+E9d6TV0BLQJypxKwufygJ1ZMzDYUntJlF3gpaBlbmAXXz0ZRG6gskT3AiKqls FQgLziaiSgFbIij7fr5PgZWH0ZN0VOFLqrvggSQhuHCh9GqlnZgfgJ4WJYhBplI+e92p tWIxsqbF3q63thO9NQ3ZAlJm9DD4SYtSu7ULH0FvzWFshROa5+GDnjIFQuQBy8Dyhuvj vcdcgPs8fBGgE03XAlczSbYn3oFxeszqKeJUp/Fczhm6nYh/0v2Kmy8TOKQyEVASmXLx FrCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z07PPt/u97dYBnTZgvhRJ5rLo7+ZbziTOZ6KMaLiXtU=; b=Kegn8m2ZEYUQKIZC3g7luvjRylKLFUvVuLsnpvrfZEAsSO4OyvAd7FCmJtUzl+6fsO 4HtCidzRDDBnqzxzoJEAvhzMizfCCvjEe33DzoUJH1z55XDQ72ZwXZRKomuQeTtOC2Jp WWXRuSVAzbu1sIUmKzbeGW7pZ1KKTi4UeidxZvbm5PJZgkTz1zAbVSEX+Nx+V07Bv31v mylZSHjcVO25cPpN1vy3RhqLwdsqoXZJbgDzW2oL0+RP7KmlRGAMaEFuw4sfrEruznNC m5U7WrZ6KUIzzcNeFsZQaL10D8++FnaqMf7EMBF22uYE/ikwXLPA36j3XbQg4/xLpxan 06mw== X-Gm-Message-State: AOAM530suGD/Ct8txcbIQ2OCS+p3OISvGu9xCJThetP/GNms7h1GEse/ mklAaAORt+xVElwpfVw0I2K/UIx1 X-Google-Smtp-Source: ABdhPJxaKvBwRyTdyvk01wbXZBDYI3yeNk6swFO3Ell52B0Lg1W78KUXB4yGariWUIU0YR3GP/Pujg== X-Received: by 2002:a19:8b06:: with SMTP id n6mr10632727lfd.66.1591556241530; Sun, 07 Jun 2020 11:57:21 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id e21sm3650953ljb.135.2020.06.07.11.57.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jun 2020 11:57:21 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v3 09/39] memory: tegra20-emc: Initialize MC timings Date: Sun, 7 Jun 2020 21:55:00 +0300 Message-Id: <20200607185530.18113-10-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200607185530.18113-1-digetx@gmail.com> References: <20200607185530.18113-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org We're going to add interconnect support to the EMC driver. Once this support will be added, the Tegra20 devfreq driver will no longer be able to use clk_round_rate(emc) for building up OPP table. It's quite handy that struct tegra_mc contains memory timings which could be used by the devfreq drivers instead of the clk rate-rounding. The tegra_mc timings are populated by the MC driver only for Tegra30+ SoCs, hence the Tegra20 EMC could populate timings by itself. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 47 ++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 035d9251e28a..a95522020a25 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -15,12 +15,15 @@ #include #include #include +#include #include #include #include #include +#include "mc.h" + #define EMC_INTSTATUS 0x000 #define EMC_INTMASK 0x004 #define EMC_DBG 0x008 @@ -650,6 +653,38 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static int tegra_emc_init_mc_timings(struct tegra_emc *emc) +{ + struct tegra_mc_timing *timing; + struct platform_device *pdev; + struct device_node *np; + struct tegra_mc *mc; + unsigned int i; + + np = of_find_compatible_node(NULL, NULL, "nvidia,tegra20-mc-gart"); + if (!np) + return -ENOENT; + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return -ENOENT; + + mc = platform_get_drvdata(pdev); + if (!mc) + return -EPROBE_DEFER; + + mc->timings = devm_kcalloc(mc->dev, emc->num_timings, sizeof(*timing), + GFP_KERNEL); + if (!mc->timings) + return -ENOMEM; + + for (i = 0; i < emc->num_timings; i++) + mc->timings[mc->num_timings++].rate = emc->timings[i].rate; + + return 0; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -705,6 +740,18 @@ static int tegra_emc_probe(struct platform_device *pdev) return err; } + /* + * Only Tegra30+ SoCs are having Memory Controller timings initialized + * by the MC driver. For Tegra20 we need to populate the MC timings + * from here. The MC timings will be used by the Tegra20 devfreq driver. + */ + err = tegra_emc_init_mc_timings(emc); + if (err) { + dev_err(&pdev->dev, "failed to initialize mc timings: %d\n", + err); + return err; + } + tegra20_clk_set_emc_round_callback(emc_round_rate, emc); emc->clk = devm_clk_get(&pdev->dev, "emc");