| Message ID | 20200310152003.2945170-2-thierry.reding@gmail.com |
|---|---|
| State | Deferred |
| Headers | show |
| Series | Add EMC scaling support for Tegra210 | expand |
10.03.2020 18:19, Thierry Reding пишет: > From: Joseph Lo <josephl@nvidia.com> > > Introduce the low jitter path of PLLP and PLLMB which can be used as EMC > clock source. > > Signed-off-by: Joseph Lo <josephl@nvidia.com> > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/clk/tegra/clk-tegra210.c | 11 +++++++++++ > include/dt-bindings/clock/tegra210-car.h | 4 ++-- > 2 files changed, 13 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c > index 45d54ead30bc..f99647b4a71f 100644 > --- a/drivers/clk/tegra/clk-tegra210.c > +++ b/drivers/clk/tegra/clk-tegra210.c > @@ -3161,6 +3161,17 @@ static void __init tegra210_pll_init(void __iomem *clk_base, > clk_register_clkdev(clk, "pll_m_ud", NULL); > clks[TEGRA210_CLK_PLL_M_UD] = clk; > > + /* PLLMB_UD */ > + clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb", > + CLK_SET_RATE_PARENT, 1, 1); > + clk_register_clkdev(clk, "pll_mb_ud", NULL); > + clks[TEGRA210_CLK_PLL_MB_UD] = clk; > + > + /* PLLP_UD */ > + clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p", > + 0, 1, 1); > + clks[TEGRA210_CLK_PLL_P_UD] = clk; Isn't it possible to auto-enable the low-jitter bit when necessary during of the rate-change based on a given clock-rate?
On Tue, Mar 10, 2020 at 07:19:59PM +0300, Dmitry Osipenko wrote: > 10.03.2020 18:19, Thierry Reding пишет: > > From: Joseph Lo <josephl@nvidia.com> > > > > Introduce the low jitter path of PLLP and PLLMB which can be used as EMC > > clock source. > > > > Signed-off-by: Joseph Lo <josephl@nvidia.com> > > Signed-off-by: Thierry Reding <treding@nvidia.com> > > --- > > drivers/clk/tegra/clk-tegra210.c | 11 +++++++++++ > > include/dt-bindings/clock/tegra210-car.h | 4 ++-- > > 2 files changed, 13 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c > > index 45d54ead30bc..f99647b4a71f 100644 > > --- a/drivers/clk/tegra/clk-tegra210.c > > +++ b/drivers/clk/tegra/clk-tegra210.c > > @@ -3161,6 +3161,17 @@ static void __init tegra210_pll_init(void __iomem *clk_base, > > clk_register_clkdev(clk, "pll_m_ud", NULL); > > clks[TEGRA210_CLK_PLL_M_UD] = clk; > > > > + /* PLLMB_UD */ > > + clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb", > > + CLK_SET_RATE_PARENT, 1, 1); > > + clk_register_clkdev(clk, "pll_mb_ud", NULL); > > + clks[TEGRA210_CLK_PLL_MB_UD] = clk; > > + > > + /* PLLP_UD */ > > + clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p", > > + 0, 1, 1); > > + clks[TEGRA210_CLK_PLL_P_UD] = clk; > > Isn't it possible to auto-enable the low-jitter bit when necessary > during of the rate-change based on a given clock-rate? I don't think so. These new clocks (pll_mb_ud and pll_p_ud) are parents for the emc clock, so they are needed to properly reflect the position of the emc clock in the clock tree. Thierry
10.03.2020 20:05, Thierry Reding пишет: > On Tue, Mar 10, 2020 at 07:19:59PM +0300, Dmitry Osipenko wrote: >> 10.03.2020 18:19, Thierry Reding пишет: >>> From: Joseph Lo <josephl@nvidia.com> >>> >>> Introduce the low jitter path of PLLP and PLLMB which can be used as EMC >>> clock source. >>> >>> Signed-off-by: Joseph Lo <josephl@nvidia.com> >>> Signed-off-by: Thierry Reding <treding@nvidia.com> >>> --- >>> drivers/clk/tegra/clk-tegra210.c | 11 +++++++++++ >>> include/dt-bindings/clock/tegra210-car.h | 4 ++-- >>> 2 files changed, 13 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c >>> index 45d54ead30bc..f99647b4a71f 100644 >>> --- a/drivers/clk/tegra/clk-tegra210.c >>> +++ b/drivers/clk/tegra/clk-tegra210.c >>> @@ -3161,6 +3161,17 @@ static void __init tegra210_pll_init(void __iomem *clk_base, >>> clk_register_clkdev(clk, "pll_m_ud", NULL); >>> clks[TEGRA210_CLK_PLL_M_UD] = clk; >>> >>> + /* PLLMB_UD */ >>> + clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb", >>> + CLK_SET_RATE_PARENT, 1, 1); >>> + clk_register_clkdev(clk, "pll_mb_ud", NULL); >>> + clks[TEGRA210_CLK_PLL_MB_UD] = clk; >>> + >>> + /* PLLP_UD */ >>> + clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p", >>> + 0, 1, 1); >>> + clks[TEGRA210_CLK_PLL_P_UD] = clk; >> >> Isn't it possible to auto-enable the low-jitter bit when necessary >> during of the rate-change based on a given clock-rate? > > I don't think so. These new clocks (pll_mb_ud and pll_p_ud) are parents > for the emc clock, so they are needed to properly reflect the position > of the emc clock in the clock tree. Okay, even if it's possible to do, I guess that won't be very compatible with the firmware.
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 45d54ead30bc..f99647b4a71f 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3161,6 +3161,17 @@ static void __init tegra210_pll_init(void __iomem *clk_base, clk_register_clkdev(clk, "pll_m_ud", NULL); clks[TEGRA210_CLK_PLL_M_UD] = clk; + /* PLLMB_UD */ + clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb", + CLK_SET_RATE_PARENT, 1, 1); + clk_register_clkdev(clk, "pll_mb_ud", NULL); + clks[TEGRA210_CLK_PLL_MB_UD] = clk; + + /* PLLP_UD */ + clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p", + 0, 1, 1); + clks[TEGRA210_CLK_PLL_P_UD] = clk; + /* PLLU_VCO */ if (!tegra210_init_pllu()) { clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0, diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 7a8f10b9a66d..5c93b01156d4 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -351,8 +351,8 @@ #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 #define TEGRA210_CLK_XUSB_SSP_SRC 318 #define TEGRA210_CLK_PLL_RE_OUT1 319 -/* 320 */ -/* 321 */ +#define TEGRA210_CLK_PLL_MB_UD 320 +#define TEGRA210_CLK_PLL_P_UD 321 #define TEGRA210_CLK_ISP 322 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324