diff mbox series

[V6,07/27] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability

Message ID 20190618180206.4908-8-mmaddireddy@nvidia.com
State Deferred
Headers show
Series Enable Tegra PCIe root port features | expand

Commit Message

Manikanta Maddireddy June 18, 2019, 6:01 p.m. UTC 
Default root port setting hides AER capability. This patch enables the
advertisement of AER capability by root port.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
V6: No change

V5: No change

V4: No change

V3: No change

V2: No change

 drivers/pci/controller/pci-tegra.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Nicolas Chauvet Jan. 15, 2020, 10:13 p.m. UTC | #1 
Le mar. 18 juin 2019 à 20:02, Manikanta Maddireddy
<mmaddireddy@nvidia.com> a écrit :
>
> Default root port setting hides AER capability. This patch enables the
> advertisement of AER capability by root port.

Hello,

For your information, I've reported an issue on kernel.org that is
related to AER in pcie with the ethernet NIC on jetson-tk1
https://bugzilla.kernel.org/show_bug.cgi?id=206217

I hope someone can shred some lights on this.
Manikanta Maddireddy Jan. 19, 2020, 10:13 a.m. UTC | #2 
On 16-Jan-20 3:43 AM, Nicolas Chauvet wrote:
> External email: Use caution opening links or attachments
>
>
> Le mar. 18 juin 2019 à 20:02, Manikanta Maddireddy
> <mmaddireddy@nvidia.com> a écrit :
>> Default root port setting hides AER capability. This patch enables the
>> advertisement of AER capability by root port.
> Hello,
>
> For your information, I've reported an issue on kernel.org that is
> related to AER in pcie with the ethernet NIC on jetson-tk1
> https://bugzilla.kernel.org/show_bug.cgi?id=206217
>
> I hope someone can shred some lights on this.
>
> --
> -
>
> Nicolas (kwizart)

Hi Nicolas,

This patch enables error reporting capability, it shouldn't have caused
"NETDEV WATCHDOG" error. Let us follow up on the issue in kernel.org.

Thanks,
Manikanta
diff mbox series

Patch

diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 5d19067f7193..39a8cbf6da24 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -180,6 +180,9 @@ 
 #define RP_VEND_XP	0x00000f00
 #define  RP_VEND_XP_DL_UP	(1 << 30)
 
+#define RP_VEND_CTL1	0x00000f48
+#define  RP_VEND_CTL1_ERPT	(1 << 13)
+
 #define RP_VEND_CTL2 0x00000fa8
 #define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)
 
@@ -479,6 +482,16 @@  static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
 	afi_writel(port->pcie, value, ctrl);
 }
 
+static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
+{
+	u32 value;
+
+	/* Enable AER capability */
+	value = readl(port->base + RP_VEND_CTL1);
+	value |= RP_VEND_CTL1_ERPT;
+	writel(value, port->base + RP_VEND_CTL1);
+}
+
 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
 {
 	unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
@@ -503,6 +516,8 @@  static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
 		value |= RP_VEND_CTL2_PCA_ENABLE;
 		writel(value, port->base + RP_VEND_CTL2);
 	}
+
+	tegra_pcie_enable_rp_features(port);
 }
 
 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)