From patchwork Mon Jun 17 17:39:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 1117196 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="JEgwnVr+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45SJQh4NHtz9sDX for ; Tue, 18 Jun 2019 03:40:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728417AbfFQRko (ORCPT ); Mon, 17 Jun 2019 13:40:44 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:10910 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725995AbfFQRko (ORCPT ); Mon, 17 Jun 2019 13:40:44 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 17 Jun 2019 10:40:42 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 17 Jun 2019 10:40:43 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 17 Jun 2019 10:40:43 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 17 Jun 2019 17:40:42 +0000 Received: from manikanta-bm2.nvidia.com (10.124.1.5) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 17 Jun 2019 17:40:39 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V5 13/27] PCI: tegra: Increase the deskew retry time Date: Mon, 17 Jun 2019 23:09:38 +0530 Message-ID: <20190617173952.29363-14-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190617173952.29363-1-mmaddireddy@nvidia.com> References: <20190617173952.29363-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560793243; bh=vj5KVAs/9jGyZFxyso2KH/65Ltg80B89X8yn8K7AdUQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=JEgwnVr+9i7dau/Sz5E1kaltwIiPfm88doecV9YfWIz9TDG3j6GuIe3SAbdm/TCdv 0dGC7b0EIkIrrM4VdAfg9RIHBjnf4PVQdDyZzkMUAnzrFMvbPto6hVfUIUpXT2Hgj0 4z4gFcLQCUfH5bYH4xRumZa5AD8PDAr9ViAJMMzdWg9ciagTypUpzCChJoZUrrpMHC PmhelR2goJqmRRB5qP332i/pXzEF8lI8kPzfPpGOzD0YEA2vjQRTayMArEb1u68BAs WO/B20zc0ENjJ95/Zvxq7NtfMimOCcsumh9jSQwxl2kzWPR+bEffMsC23JD2pWzKmN xkG+Rek81mRyw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Sometimes link speed change from Gen2 to Gen1 fails due to instability in deskew logic on lane-0 in Tegra210. Increase the deskew retry time to resolve this issue. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V5: No change V4: No change V3: No change V2: Took care of typos in commit log and coding style comments. drivers/pci/controller/pci-tegra.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index add649d91e7c..6f06327ca0aa 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -209,6 +209,10 @@ #define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) +#define RP_VEND_CTL0 0x00000f44 +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) +#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12) + #define RP_VEND_CTL1 0x00000f48 #define RP_VEND_CTL1_ERPT (1 << 13) @@ -305,6 +309,7 @@ struct tegra_pcie_soc { bool force_pca_enable; bool program_uphy; bool update_clamp_threshold; + bool program_deskew_time; struct { struct { u32 rp_ectl_2_r1; @@ -620,6 +625,24 @@ static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port) writel(value, port->base + RP_ECTL_6_R2); } +static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) +{ + const struct tegra_pcie_soc *soc = port->pcie->soc; + u32 value; + + /* + * Sometimes link speed change from Gen2 to Gen1 fails due to + * instability in deskew logic on lane-0. Increase the deskew + * retry time to resolve this issue. + */ + if (soc->program_deskew_time) { + value = readl(port->base + RP_VEND_CTL0); + value &= ~RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK; + value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH; + writel(value, port->base + RP_VEND_CTL0); + } +} + static void tegra_pcie_port_enable(struct tegra_pcie_port *port) { unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); @@ -649,6 +672,8 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port) if (soc->ectl.enable) tegra_pcie_program_ectl_settings(port); + + tegra_pcie_apply_sw_fixup(port); } static void tegra_pcie_port_disable(struct tegra_pcie_port *port) @@ -2356,6 +2381,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .force_pca_enable = false, .program_uphy = true, .update_clamp_threshold = false, + .program_deskew_time = false, .ectl.enable = false, }; @@ -2381,6 +2407,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .force_pca_enable = false, .program_uphy = true, .update_clamp_threshold = false, + .program_deskew_time = false, .ectl.enable = false, }; @@ -2399,6 +2426,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .force_pca_enable = false, .program_uphy = true, .update_clamp_threshold = true, + .program_deskew_time = false, .ectl.enable = false, }; @@ -2417,6 +2445,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .force_pca_enable = true, .program_uphy = true, .update_clamp_threshold = true, + .program_deskew_time = true, .ectl = { .regs = { .rp_ectl_2_r1 = 0x0000000f, @@ -2454,6 +2483,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .force_pca_enable = false, .program_uphy = false, .update_clamp_threshold = false, + .program_deskew_time = false, .ectl.enable = false, };