From patchwork Thu May 16 05:52:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 1100318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="luHWZqBI"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 454LFt3GTZz9sN1 for ; Thu, 16 May 2019 15:53:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726379AbfEPFxy (ORCPT ); Thu, 16 May 2019 01:53:54 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15032 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726277AbfEPFxx (ORCPT ); Thu, 16 May 2019 01:53:53 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 15 May 2019 22:53:48 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 15 May 2019 22:53:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 15 May 2019 22:53:53 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 16 May 2019 05:53:52 +0000 Received: from manikanta-bm2.nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 16 May 2019 05:53:49 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V4 11/28] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Date: Thu, 16 May 2019 11:22:50 +0530 Message-ID: <20190516055307.25737-12-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190516055307.25737-1-mmaddireddy@nvidia.com> References: <20190516055307.25737-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557986029; bh=lzW1KXbPv4AzjH8K+0PAaMVYL5T+fybrcbfuiPNv9cc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=luHWZqBIqHx/BQy6kyb4f5tApwGHTXS0AM0UeFUw6UzO2yTsBkhVTPJQyYx3DTxYv fL4Uy2Kx6GTiEn7ht0yO6p4ymFbzRx7uQwoum/LeQ3GdhtmLxGHXU/i/y0FriuPkXy ZjPEQiAv/QgP+IfWVBapk6wSR9Kj4LSRUjcR5qfm9YGlflpKL24KbkeotnvWIpQDtN zZGZVynmG5JNxZMklGsI9LNv7PqoLKMGKJN5QjKoeSqYmJPpoh8yW4M55wBL1uI5bs yX7glVTYqObg/e66iIndvLQy9G9uoQdVl62Jo75CgRit5QRIBTjI092vYZCacMCdb0 Lck6zCyc8N2Vg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org PM message are truncated while entering L1 or L2, which is resulting in receiver errors. Set the required bit to finish processing DLLP before link enter L1 or L2. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V4: No change V3: No change V2: No change drivers/pci/controller/pci-tegra.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 17c6d858ddc6..d3da03a10e04 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -212,6 +212,9 @@ #define RP_VEND_CTL1 0x00000f48 #define RP_VEND_CTL1_ERPT (1 << 13) +#define RP_VEND_XP_BIST 0x00000f4c +#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28) + #define RP_VEND_CTL2 0x00000fa8 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) @@ -538,6 +541,14 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) value |= RP_VEND_XP_OPPORTUNISTIC_ACK; value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC; writel(value, port->base + RP_VEND_XP); + + /* + * LTSSM will wait for DLLP to finish before entering L1 or L2, + * to avoid truncation of PM messages which results in receiver errors + */ + value = readl(port->base + RP_VEND_XP_BIST); + value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE; + writel(value, port->base + RP_VEND_XP_BIST); } static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)