From patchwork Thu Apr 18 11:12:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Gorski X-Patchwork-Id: 1087517 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="R4nTJkPa"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44lGfC6P0sz9s3Z for ; Thu, 18 Apr 2019 21:12:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388401AbfDRLMT (ORCPT ); Thu, 18 Apr 2019 07:12:19 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:38820 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388375AbfDRLMT (ORCPT ); Thu, 18 Apr 2019 07:12:19 -0400 Received: by mail-wm1-f65.google.com with SMTP id w15so2420164wmc.3; Thu, 18 Apr 2019 04:12:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cm1EEGeZHsHeXdzknWNTewmHAGGaI1nGB6a7qRF/P7c=; b=R4nTJkPaGbHzkHhLqaoceUHq8NlF7Zxf8cy/R8GkIIKkUNdpxa1NUHv17CvdbutIuJ gpFKHKIEBWpsQGr8jtRBZignnQ4OumyZ73y9kJ6bBfx/a/dynf8FIBQDkcBuRJ2FN0LQ L8Ex8y/vjyBvap22CEh0VTK6oBsW7Rq1NJZmqriHu4Aq58nv2dMgMOI4IOSNc0zAmrhg 8fy9fNjEtiRREKSSI9DGE4VA1CN/rNiB+IqQN29LynUINmMeyv2xjTyp2tnCVMm7+PjI ntSvwuT2WmPsXmA0DUGUd2UtuuSQ5WaKzXb7OoVlykK/+DQy3OBK5Wv0xJ0teJGAV9nM 5DBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cm1EEGeZHsHeXdzknWNTewmHAGGaI1nGB6a7qRF/P7c=; b=J5x0ehVuHyTuFJUh07R49QkTUjBGdPTuAXZ1zlQAW/ANGyj2AttxKb1cSTq7+URznN DG30N5lSWKVmMaZTdeZe2sFVIUctqAnGJhvWL0T/vKZa29WeJPNpIEOxOyniqUCQHAX0 AZuP9v7KQsPvNvQz934IoIQIvYkPwv+Q8t9tIpBsvczIxxEX598+Bdao2MxNO2SRn6WS mnquKnvdtpPkVcCh9y23h2/T8gZQGhiPXPuZM1rtbZHeDlibkSUzl7PayldFJsV/dzQG kKp45TWdeuvPR+9Es13eC0JWwvqoQb1DpJiv+YmLnOHjmMvVNZv8Qj1G6yqH2mJgiWL6 nxNQ== X-Gm-Message-State: APjAAAXZ7Pd5vPZ2NJUEwkIKdrW5l/4nifFn5eZ2I+D0xpytclj4g8+3 dGkfCngoeDWGhG2XeLlVVHuuGphP1tU= X-Google-Smtp-Source: APXvYqzcxqiH4NfwjdJ93Bud895D2LmZXnP6SukbgtmppxptpSRARrAOSdr4F5mOJgEaaReIeCmaJQ== X-Received: by 2002:a1c:3d6:: with SMTP id 205mr2873697wmd.66.1555585937030; Thu, 18 Apr 2019 04:12:17 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id z63sm2005594wme.30.2019.04.18.04.12.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Apr 2019 04:12:16 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Cc: Anatolij Gustschin , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Heiko Stuebner , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Michal Simek Subject: [PATCH RFT V3 2/8] clk: fractional-divider: add explicit big endian support Date: Thu, 18 Apr 2019 13:12:05 +0200 Message-Id: <20190418111211.10474-3-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190418111211.10474-1-jonas.gorski@gmail.com> References: <20190418111211.10474-1-jonas.gorski@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add a clock specific flag to switch register accesses to big endian, to allow runtime configuration of big endian fractional divider clocks. Signed-off-by: Jonas Gorski --- V2 -> V3: * drop unneeded else in clk_fd_readl V1 -> V2: * switch from global to local flag drivers/clk/clk-fractional-divider.c | 22 +++++++++++++++++++--- include/linux/clk-provider.h | 4 ++++ 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index fdfe2e423d15..f88df265e787 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -13,6 +13,22 @@ #include #include +static inline u32 clk_fd_readl(struct clk_fractional_divider *fd) +{ + if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN) + return ioread32be(fd->reg); + + return clk_readl(fd->reg); +} + +static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val) +{ + if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN) + iowrite32be(val, fd->reg); + else + clk_writel(val, fd->reg); +} + static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -27,7 +43,7 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, else __acquire(fd->lock); - val = clk_readl(fd->reg); + val = clk_fd_readl(fd); if (fd->lock) spin_unlock_irqrestore(fd->lock, flags); @@ -115,10 +131,10 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, else __acquire(fd->lock); - val = clk_readl(fd->reg); + val = clk_fd_readl(fd); val &= ~(fd->mmask | fd->nmask); val |= (m << fd->mshift) | (n << fd->nshift); - clk_writel(val, fd->reg); + clk_fd_writel(fd, val); if (fd->lock) spin_unlock_irqrestore(fd->lock, flags); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 7117b8cc0c0c..8c07d810acf5 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -607,6 +607,9 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED * is set then the numerator and denominator are both the value read * plus one. + * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are + * used for the divider register. Setting this flag makes the register + * accesses big endian. */ struct clk_fractional_divider { struct clk_hw hw; @@ -627,6 +630,7 @@ struct clk_fractional_divider { #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) +#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev,