diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index fa8d573ac626..c483bdb562f6 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -22,6 +22,7 @@
 #include <linux/of_address.h>
 #include <linux/clk/tegra.h>
 
+#include <soc/tegra/common.h>
 #include <soc/tegra/pmc.h>
 
 #include <dt-bindings/clock/tegra30-car.h>
@@ -1278,9 +1279,89 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
 };
 
+/* Tegra30 automotive part initialisation table.
+ *
+ * These values have been derived from the Nvidia supplied BSP for their
+ * automotive parts.
+ */
+static struct tegra_clk_init_table init_table_t30a[] __initdata = {
+	{ TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 1 },
+	{ TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 1 },
+	{ TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
+	{ TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 1 },
+	{ TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
+	{ TEGRA30_CLK_PLL_P_OUT1, TEGRA30_CLK_CLK_MAX, 9600000, 1 },
+	{ TEGRA30_CLK_PLL_P_OUT2, TEGRA30_CLK_CLK_MAX, 48000000, 1 },
+	{ TEGRA30_CLK_PLL_P_OUT3, TEGRA30_CLK_CLK_MAX, 102000000, 1 },
+	{ TEGRA30_CLK_PLL_P_OUT4, TEGRA30_CLK_CLK_MAX, 102000000, 1 },
+	{ TEGRA30_CLK_FUSE, TEGRA30_CLK_CLK_MAX, 12000000, 1 },
+	{ TEGRA30_CLK_KFUSE, TEGRA30_CLK_CLK_MAX, 12000000, 1 },
+	{ TEGRA30_CLK_CCLK_G, TEGRA30_CLK_CLK_MAX, 900000000, 0 },
+	{ TEGRA30_CLK_CCLK_LP,TEGRA30_CLK_CLK_MAX, 484000000, 0 },
+	{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 552960000, 1 },
+	{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 24576000, 1 },
+	{ TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 24576000, 1 },
+	{ TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_CLK_M, 0, 0 },
+	{ TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 },
+	{ TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 },
+	{ TEGRA30_CLK_I2S0, TEGRA30_CLK_CLK_M, 12288000, 0 },
+	{ TEGRA30_CLK_I2S1, TEGRA30_CLK_CLK_M, 12288000, 0 },
+	{ TEGRA30_CLK_I2S2, TEGRA30_CLK_CLK_M, 12288000, 0 },
+	{ TEGRA30_CLK_I2S3, TEGRA30_CLK_CLK_M, 12288000, 0 },
+	{ TEGRA30_CLK_I2S4, TEGRA30_CLK_CLK_M, 12288000, 0 },
+	{ TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 108000000, 0 },
+	{ TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
+	{ TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
+	{ TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 104000000, 0 },
+	{ TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
+	{ TEGRA30_CLK_SDMMC4, TEGRA30_CLK_PLL_P, 48000000, 0 },
+	{ TEGRA30_CLK_NOR, TEGRA30_CLK_PLL_P, 102000000, 0 },
+	{ TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
+	{ TEGRA30_CLK_PLL_M_OUT1, TEGRA30_CLK_CLK_MAX, 312500000, 1 },
+	{ TEGRA30_CLK_SCLK, TEGRA30_CLK_PLL_M_OUT1, 312500000, 1 },
+	{ TEGRA30_CLK_HCLK, TEGRA30_CLK_CLK_MAX, 312500000, 1 },
+	{ TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 312500000/2, 1 },
+	{ TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
+	{ TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 },
+	{ TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
+	{ TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 484000000, 1 },
+	/* initialse PLL_D and set it up before the display code for test */
+	{ TEGRA30_CLK_PLL_D, TEGRA30_CLK_CLK_MAX, 257800000, 1 },
+	/* set EPP clock to TEGRA30_CLK_PLL_C */
+	{ TEGRA30_CLK_EPP, TEGRA30_CLK_PLL_C, 484000000, 0 },
+	{ TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_M, 15822784, 1 },
+	{ TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_M, 100000000, 1 },
+	{ TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_M, 100000000, 1 },
+	{ TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_M, 100000000, 1 },
+	{ TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_M, 100000000, 1 },
+	{ TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_M, 100000000, 1 },
+	{ TEGRA30_CLK_SE, TEGRA30_CLK_PLL_M, 625000000, 1 },
+	{ TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 242000000, 0 },
+	{ TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 275000000, 0 },
+	{ TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 275000000, 0 },
+	{ TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
+	{ TEGRA30_CLK_GR2D, TEGRA30_CLK_CLK_MAX, 484000000, 0 },
+	{ TEGRA30_CLK_GR3D, TEGRA30_CLK_CLK_MAX, 484000000, 0 },
+	{ TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 484000000, 0 },
+	{ TEGRA30_CLK_D_AUDIO, TEGRA30_CLK_PLL_A_OUT0, 24576000, 0 },
+	{ TEGRA30_CLK_MPE, TEGRA30_CLK_PLL_C, 484000000, 0 },
+	{ TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 484000000, 0 },
+	{ TEGRA30_CLK_VI, TEGRA30_CLK_PLL_P, 470000000, 0 },
+	{ TEGRA30_CLK_VI_SENSOR, TEGRA30_CLK_PLL_P, 150000000, 0 },
+	{ TEGRA30_CLK_PWM, TEGRA30_CLK_CLK_32K, 32768, 0 },
+	{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, /* This MUST be the last entry. */
+};
+
 static void __init tegra30_clock_apply_init_table(void)
 {
-	tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
+	struct tegra_clk_init_table *table = init_table;
+
+	if (soc_is_tegra_auto()) {
+		pr_info("Initialise Tegra Automotive clocks\n");
+		table = init_table_t30a;
+	}
+
+	tegra_init_from_table(table, clks, TEGRA30_CLK_CLK_MAX);
 }
 
 /*
