[v3,16/16] arm64: tegra: Enable SMMU for VIC on Tegra186

Message ID	20190201132837.12327-17-thierry.reding@gmail.com
State	Deferred
Headers	show Return-Path: <linux-tegra-owner@vger.kernel.org> From: Thierry Reding <thierry.reding@gmail.com> To: Thierry Reding <thierry.reding@gmail.com> Cc: Mikko Perttunen <mperttunen@nvidia.com>, Dmitry Osipenko <digetx@gmail.com>, dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH v3 16/16] arm64: tegra: Enable SMMU for VIC on Tegra186 Date: Fri, 1 Feb 2019 14:28:37 +0100 Message-Id: <20190201132837.12327-17-thierry.reding@gmail.com> In-Reply-To: <20190201132837.12327-1-thierry.reding@gmail.com> References: <20190201132837.12327-1-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk
Series	drm/tegra: Fix IOVA space on Tegra186 and later \| expand [v3,00/16] drm/tegra: Fix IOVA space on Tegra186 and later [v3,01/16] gpu: host1x: Set up stream ID table [v3,02/16] gpu: host1x: Program the channel stream ID [v3,03/16] gpu: host1x: Introduce support for wide opcodes [v3,04/16] gpu: host1x: Support 40-bit addressing [v3,05/16] gpu: host1x: Use direct DMA with IOMMU API usage [v3,06/16] gpu: host1x: Restrict IOVA space to DMA mask [v3,07/16] gpu: host1x: Support 40-bit addressing on Tegra186 [v3,08/16] gpu: host1x: Use correct semantics for HOST1X_CHANNEL_DMAEND [v3,09/16] gpu: host1x: Optimize CDMA push buffer memory usage [v3,10/16] drm/tegra: Store parent pointer in Tegra DRM clients [v3,11/16] drm/tegra: vic: Load firmware on demand [v3,12/16] drm/tegra: Setup shared IOMMU domain after initialization [v3,13/16] drm/tegra: Restrict IOVA space to DMA mask [v3,14/16] drm/tegra: vic: Do not clear driver data [v3,15/16] drm/tegra: vic: Support stream ID register programming [v3,16/16] arm64: tegra: Enable SMMU for VIC on Tegra186

Message ID

20190201132837.12327-17-thierry.reding@gmail.com

State

Deferred

Headers

From: Thierry Reding <thierry.reding@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Mikko Perttunen <mperttunen@nvidia.com>,
	Dmitry Osipenko <digetx@gmail.com>,
	dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org
Subject: [PATCH v3 16/16] arm64: tegra: Enable SMMU for VIC on Tegra186
Date: Fri,  1 Feb 2019 14:28:37 +0100
Message-Id: <20190201132837.12327-17-thierry.reding@gmail.com>
In-Reply-To: <20190201132837.12327-1-thierry.reding@gmail.com>
References: <20190201132837.12327-1-thierry.reding@gmail.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Sender: linux-tegra-owner@vger.kernel.org
Precedence: bulk

Series

drm/tegra: Fix IOVA space on Tegra186 and later | expand

Commit Message

Thierry Reding Feb. 1, 2019, 1:28 p.m. UTC

From: Thierry Reding <treding@nvidia.com>

Enable address translation for VIC via the SMMU on Tegra186.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 66ea7e7c79f5..67b9f8ed3c9b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -799,6 +799,7 @@ 
 			reset-names = "vic";
 
 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
+			iommus = <&smmu TEGRA186_SID_VIC>;
 		};
 
 		dsib: dsi@15400000 {

[v3,16/16] arm64: tegra: Enable SMMU for VIC on Tegra186

Commit Message

Patch