From patchwork Mon Jan 7 03:28:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1021160 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="aq5tkN4O"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43Y17b1WGVz9sD4 for ; Mon, 7 Jan 2019 14:28:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726257AbfAGD2Z (ORCPT ); Sun, 6 Jan 2019 22:28:25 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:6265 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726447AbfAGD2Y (ORCPT ); Sun, 6 Jan 2019 22:28:24 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 06 Jan 2019 19:28:00 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 06 Jan 2019 19:28:23 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 06 Jan 2019 19:28:23 -0800 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 7 Jan 2019 03:28:23 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 7 Jan 2019 03:28:23 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 06 Jan 2019 19:28:23 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter CC: , , Joseph Lo Subject: [PATCH 4/6] arm64: dts: tegra210: add CPU idle states properties Date: Mon, 7 Jan 2019 11:28:08 +0800 Message-ID: <20190107032810.13522-5-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190107032810.13522-1-josephl@nvidia.com> References: <20190107032810.13522-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1546831681; bh=U0sP/oEk98P7s1jfTqtBJ8M85xm2iO063cva224c59Y=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=aq5tkN4O1UcQNqmkczxmWwX5mJaLXoeVLT6hJVR5KqC6LKf7jsVWqVFWhOVwBt1Rh WRGlo44wsUcec4QeGda464ZpbP/F4QY4UmEwOc1yn29AloALWdkI8X5HNKH8/DMX+I 1d/6F4VmnHMdbCjRW9zwh34+ILFfOP49xwLjuE1LEsi+rPGmgNx5E5JAWfcyAHNxPt zFAXD+duKjRJirZVCjArMRLTkREj2sKAEKIgGMJRgHNKIKmxnSML9mdKfYiQxxXohl jd1bMnlOIZkdRZAb1+rhC++kZqH4QS9U3Bq6lmxXcB8vkRCuHWTBeQVXYJ17YNhYx6 XPKNn1Wok8RuA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add idle states properties for generic ARM CPU idle driver. This includes a C7 state which is the power down state of CPU cores. Signed-off-by: Joseph Lo --- Note: This dt patch depends on the DT changes in below series. http://patchwork.ozlabs.org/project/linux-tegra/list/?series=84380 --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 143bd103c923..b583d3065946 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1308,24 +1308,41 @@ <&dfll>; clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; + cpu-idle-states = <&C7>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <1>; + cpu-idle-states = <&C7>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <2>; + cpu-idle-states = <&C7>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <3>; + cpu-idle-states = <&C7>; + }; + + idle-states { + entry-method = "psci"; + + C7: c7 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000007>; + wakeup-latency-us = <130>; + min-residency-us = <1000>; + idle-state-name = "c7-cpu-powergated"; + status = "disabled"; + }; }; };