| Message ID | 20181218091232.23532-5-josephl@nvidia.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Tegra210 DFLL support | expand |
On Tue, 18 Dec 2018 17:12:16 +0800, Joseph Lo wrote: > The cpu_lp clock property is only needed when the CPUfreq driver > supports CPU cluster switching. But it was not a design for this driver > and it didn't handle that as well. So removing this property. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Joseph Lo <josephl@nvidia.com> > Acked-by: Jon Hunter <jonathanh@nvidia.com> > --- > *V3: > - no change > *V2: > - add ack tag > --- > .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt index 031545a29caf..03196d5ea515 100644 --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt @@ -9,7 +9,6 @@ Required properties: See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - cpu_g: Clock mux for the fast CPU cluster. - - cpu_lp: Clock mux for the low-power CPU cluster. - pll_x: Fast PLL clocksource. - pll_p: Auxiliary PLL used during fast PLL rate changes. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. @@ -30,11 +29,10 @@ cpus { reg = <0>; clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, - <&tegra_car TEGRA124_CLK_CCLK_LP>, <&tegra_car TEGRA124_CLK_PLL_X>, <&tegra_car TEGRA124_CLK_PLL_P>, <&dfll>; - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; };