From patchwork Thu Dec 13 09:34:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1012714 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="adR1d+gr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43FpSb0x9zz9s1c for ; Thu, 13 Dec 2018 20:35:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727969AbeLMJf0 (ORCPT ); Thu, 13 Dec 2018 04:35:26 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8188 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727754AbeLMJf0 (ORCPT ); Thu, 13 Dec 2018 04:35:26 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 01:35:20 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:35:25 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 13 Dec 2018 01:35:25 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:35:24 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:35:24 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 13 Dec 2018 01:35:24 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH V2 15/21] arm64: dts: tegra210: add DFLL clock Date: Thu, 13 Dec 2018 17:34:32 +0800 Message-ID: <20181213093438.29621-16-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com> References: <20181213093438.29621-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693720; bh=+3Vx/DlfWU2fKhmt7pa+Chw+HZ0IOJ3VH6VwZmczcrs=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=adR1d+grZ4gOLfgiIB65bKsZ/pMQAePxrjab2cE2P15+X9ANe0nmn2hD+WwnayOhe 8+J0xdaGWFkFx1zBmcp583Qgjto2NGjvnkJr/+JylU/MdAG3rOi2+qkDDN15lqfQS8 pS5dxDc4RLZW+EWCzvoP+CBnGdduKd24G2oyorAx+bEuCPiXkrvbKzYodctusX6/JA uX/+mUvD1w6tf3HAeP6xw7V664lCJxG6IaHCtRnwLLYeNQSu4YgMWGUBEnudLZuGMF juIVPKr+PSKn8WtFZ6mNLHUAaUcRwExDBPAoqf3SrxaqrsXuokCbhQ9KLDYT7RMp9W SHuH6LImLDU7A== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add essential DFLL clock properties for Tegra210. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- *V2: - add ack tag --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 2205d66b0443..a6db62157442 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -1131,6 +1132,24 @@ #nvidia,mipi-calibrate-cells = <1>; }; + dfll: clock@70110000 { + compatible = "nvidia,tegra210-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, + <&tegra_car TEGRA210_CLK_DFLL_REF>, + <&tegra_car TEGRA210_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + status = "disabled"; + }; + aconnect@702c0000 { compatible = "nvidia,tegra210-aconnect"; clocks = <&tegra_car TEGRA210_CLK_APE>,