From patchwork Thu Dec 6 18:00:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1008954 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Cebiq1Ak"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 439k0R1LvRz9s3q for ; Fri, 7 Dec 2018 05:00:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726086AbeLFSAW (ORCPT ); Thu, 6 Dec 2018 13:00:22 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:54508 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725921AbeLFSAW (ORCPT ); Thu, 6 Dec 2018 13:00:22 -0500 Received: by mail-wm1-f67.google.com with SMTP id z18so1877426wmc.4 for ; Thu, 06 Dec 2018 10:00:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hXa0u2z+u4RP/UhFpBshEV/rQZToeD2sVTxFwQyPjzc=; b=Cebiq1AkAtZdG5qaxLo2IL9dermo63VwCxHKCM95gRwxl9bG35uDgd29Rz6WdGHxQe 9rjL0P9/YDC+B2jOCCMZ3HMR2IA2sNZjqYNb6opeb7Mys163DykxmOyODRdkmE4PBfMd 5F8rpJy+IA3ysFdCF9j5+afoRfSUc5PCq0gPIgQRG8nnbXNjMYyPUjL0xujqSGjlEERA LzL+3Kn9eWChX1qzWVZGD4W1NhVuTb+ndt6rHrkUanvKN1cgUDlVBs/TfBpxd2+K85th sh6Lx/RZqstO9tut6agN9L3+Gvg8hlWqOj6HYAXfOAuR40zFRvETt6Iv5XyJc5zjY6FW ayUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hXa0u2z+u4RP/UhFpBshEV/rQZToeD2sVTxFwQyPjzc=; b=G7Ms91ybMoDuc4lQ+YRzD/fc/mvsZWazs2f5mmfxDXhiZSSGgPdJvyN+ahtc3yxKqr DOSIGc1W8yjVqe7DQOVsq8LtbmFBzkI8bPFc9jiNQ1B9y13XsqKPNdHsZt91wEMzNfvb FgPMeOpTdiEqmMJlPlm8zF3QOdPRd4GrNo/KcJo/WJ0EARCpqMczYa3zbXgAwmt+w0Su dwJDCroXCA5CP8uAxOzHAfutKyDkUfbxy3BFqLomba5u8zN5p2/FjuW8nPIuaklqJU+s pP4mornv90AJUCyBLgR0P8PaeP6Nhyf1xHlb3iJ6FfYzvKDzWsWRumT5ChLPIfr2xwDS HT1g== X-Gm-Message-State: AA+aEWbnyxIPhwyjL+nBdX6zfaJUPM2YxpRAHPPbIKn04xM8Z9nmZy+j NXM8ItTN/8O3umEPyFamoDA= X-Google-Smtp-Source: AFSGD/Vcaa8gvajvr6AFFM64q/fGVvLsPLoy/pQdcjTv/jE//N+9XS2gGkPRoXy+8T27ZhhiFMzUfA== X-Received: by 2002:a1c:7706:: with SMTP id t6mr19323258wmi.57.1544119220635; Thu, 06 Dec 2018 10:00:20 -0800 (PST) Received: from localhost (pD9E51040.dip0.t-ipconnect.de. [217.229.16.64]) by smtp.gmail.com with ESMTPSA id t18sm699164wmt.35.2018.12.06.10.00.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Dec 2018 10:00:19 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 2/2] arm64: tegra: Set reg property for display-hub on Tegra194 Date: Thu, 6 Dec 2018 19:00:17 +0100 Message-Id: <20181206180017.29918-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181206180017.29918-1-thierry.reding@gmail.com> References: <20181206180017.29918-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Technically the display-hub driver could access registers via the specified region, though it practice it will do so via the display controllers' register regions. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 31add2e2ac1b..edb8795a6ed3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -496,6 +496,7 @@ display-hub@15200000 { compatible = "nvidia,tegra194-display", "simple-bus"; + reg = <0x15200000 0x00040000>; resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,