| Message ID | 20180720134532.13148-3-ben.dooks@codethink.co.uk |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [1/8] clk: tegra: implement reset status callback | expand |
On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote: > The host1x clock according to both tegra2 and tegra3 manuals is > an 8bit divider with lsb being fractional. This is running into > an issue where the host1x is being set on a tegra20a system to > 266.4MHz but ends up at 222MHz instead. > The fact the hw has a fractional divider, does not mean we're allowed to use it. Due to the non 50% duty cycle of fractional divided clocks, they are not allowed for certain peripherals. Do you have information indicating this is ok for the host1x clock? Peter. > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> > --- > drivers/clk/tegra/clk-tegra-periph.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c > index 2acba2986bc6..8fa1cecf18a0 100644 > --- a/drivers/clk/tegra/clk-tegra-periph.c > +++ b/drivers/clk/tegra/clk-tegra-periph.c > @@ -644,7 +644,7 @@ static struct tegra_periph_init_data periph_clks[] = { > INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde), > INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi), > INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp), > - INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x), > + MUX("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x), > INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe), > INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d), > INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d), > -- > 2.18.0 > -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 2018-07-23 09:50, Peter De Schrijver wrote: > On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote: >> The host1x clock according to both tegra2 and tegra3 manuals is >> an 8bit divider with lsb being fractional. This is running into >> an issue where the host1x is being set on a tegra20a system to >> 266.4MHz but ends up at 222MHz instead. >> > > The fact the hw has a fractional divider, does not mean we're allowed > to use > it. Due to the non 50% duty cycle of fractional divided clocks, they > are not > allowed for certain peripherals. Do you have information indicating > this is > ok for the host1x clock? Only that's what was setup for the systems we're using. We couldn't match the 2.6 working system without these changes.
On Mon, Jul 23, 2018 at 10:32:58AM +0100, Ben Dooks wrote: > > > On 2018-07-23 09:50, Peter De Schrijver wrote: > >On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote: > >>The host1x clock according to both tegra2 and tegra3 manuals is > >>an 8bit divider with lsb being fractional. This is running into > >>an issue where the host1x is being set on a tegra20a system to > >>266.4MHz but ends up at 222MHz instead. > >> > > > >The fact the hw has a fractional divider, does not mean we're > >allowed to use > >it. Due to the non 50% duty cycle of fractional divided clocks, > >they are not > >allowed for certain peripherals. Do you have information > >indicating this is > >ok for the host1x clock? > > Only that's what was setup for the systems we're using. > We couldn't match the 2.6 working system without these changes. > On Tegra20 or Tegra30? Peter. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 2018-07-23 12:12, Peter De Schrijver wrote: > On Mon, Jul 23, 2018 at 10:32:58AM +0100, Ben Dooks wrote: >> >> >> On 2018-07-23 09:50, Peter De Schrijver wrote: >> >On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote: >> >>The host1x clock according to both tegra2 and tegra3 manuals is >> >>an 8bit divider with lsb being fractional. This is running into >> >>an issue where the host1x is being set on a tegra20a system to >> >>266.4MHz but ends up at 222MHz instead. >> >> >> > >> >The fact the hw has a fractional divider, does not mean we're >> >allowed to use >> >it. Due to the non 50% duty cycle of fractional divided clocks, >> >they are not >> >allowed for certain peripherals. Do you have information >> >indicating this is >> >ok for the host1x clock? >> >> Only that's what was setup for the systems we're using. >> We couldn't match the 2.6 working system without these changes. >> > > On Tegra20 or Tegra30? I'll check tomorrow when I have access to all the hw involved.
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index 2acba2986bc6..8fa1cecf18a0 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -644,7 +644,7 @@ static struct tegra_periph_init_data periph_clks[] = { INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde), INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi), INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp), - INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x), + MUX("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x), INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe), INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d), INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d),
The host1x clock according to both tegra2 and tegra3 manuals is an 8bit divider with lsb being fractional. This is running into an issue where the host1x is being set on a tegra20a system to 266.4MHz but ends up at 222MHz instead. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> --- drivers/clk/tegra/clk-tegra-periph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)