From patchwork Fri Oct 13 15:49:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 825540 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pmnIqX5w"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yDC0s0M20z9sRm for ; Sat, 14 Oct 2017 02:53:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758586AbdJMPtb (ORCPT ); Fri, 13 Oct 2017 11:49:31 -0400 Received: from mail-qk0-f193.google.com ([209.85.220.193]:45261 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757998AbdJMPt2 (ORCPT ); Fri, 13 Oct 2017 11:49:28 -0400 Received: by mail-qk0-f193.google.com with SMTP id f199so5522852qke.2; Fri, 13 Oct 2017 08:49:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6Nn9sOETsFhZljYsryp7HueCYNA7JIeDcHBw3iDShK8=; b=pmnIqX5wcmULe46FUClgMB9gpCK+eqA4Yv1GAjEqjpBeOMhtp42e0FbuSudDPM+OgX gVI1m+9TCllMeyB+5rXSzaOPbSVEq6iUdc9a1fUYobHLP/dfsvp4CrvSMFewcn1mHuQm iVbSECS+OYmPYVHSrRQ3sqgXc9bkHEblu7O7ethYPm+U2bJTt+ghEOPC4gvZWqoIhYDL hPz+OqSnbw2qOeZP4FpvBzLN5jObdamtHH/JJqYgjvi9UROVtIMmPgrZEfL8fW46ikfF qVLNztGTk6xc7cz6S55Vw4C7g8iWhOnWUDQf7WxbsQjOKbePFx7yn9J2RaGTUmfBa+S9 lCEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6Nn9sOETsFhZljYsryp7HueCYNA7JIeDcHBw3iDShK8=; b=X0PIUxu+Tzhb9JYBCdN8AmGNwkhoiOB201VL/AJH3DB1LKqSfKac27VqCDBeRQ/3D0 ofibgZIvyJsH/2LVqmMLvtaFRwS/kYBP+N0vFbE5hHK2M2LAq4+MG6ikBwUk8x2NeS5m 5obU8uIY/cKxmJnT5naV4BrP13j9UGE7J3dCZZvHVKVZHR8D0YnYCTakH9hgkc9PETSg phggCmElx1GZzLnUGG0/RfkTYxFGc8ApTWRCgpgqWwOD9Go0j+ZvOokiyq4YQV4jlvvY 6cpK8tT3v2/Lwcxs6EtY4qe23NHbccuFlVEFkj99yTYkm2rSSbjY5cJa86DjeB9sIXcw sPSQ== X-Gm-Message-State: AMCzsaU6oc6mIquF/s4jzqjOE8c72Pq4WXGRRvQvWQ2GHq0LdMitGXv7 3uvMh/pjR3gGb/IU2uJVKCbXSg== X-Google-Smtp-Source: AOwi7QBQrlD9uoxdKzBES5QIzmrPtjvoS0upzancc+8VjoBTBmj6ivBoUSBky5WgU7N2NmXC5Vjk4w== X-Received: by 10.55.54.20 with SMTP id d20mr2678354qka.182.1507909767696; Fri, 13 Oct 2017 08:49:27 -0700 (PDT) Received: from localhost (p200300E41BE4FD00CEAD5B94E1CFD280.dip0.t-ipconnect.de. [2003:e4:1be4:fd00:cead:5b94:e1cf:d280]) by smtp.gmail.com with ESMTPSA id l20sm757141qtb.27.2017.10.13.08.49.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2017 08:49:26 -0700 (PDT) From: Thierry Reding To: Linus Walleij Cc: Jonathan Hunter , Grygorii Strashko , linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 04/13] gpio: Move irq_base to struct gpio_irq_chip Date: Fri, 13 Oct 2017 17:49:04 +0200 Message-Id: <20171013154913.29448-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013154913.29448-1-thierry.reding@gmail.com> References: <20171013154913.29448-1-thierry.reding@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 2 +- include/linux/gpio/driver.h | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index c9851bd120b4..500238d898ea 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -627,7 +627,7 @@ static void armada_37xx_irq_handler(struct irq_desc *desc) static unsigned int armada_37xx_irq_startup(struct irq_data *d) { struct gpio_chip *chip = irq_data_get_irq_chip_data(d); - int irq = d->hwirq - chip->irq_base; + int irq = d->hwirq - chip->irq.first; /* * The mask field is a "precomputed bitmask for accessing the * chip registers" which was introduced for the generic diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 794bc6058282..20a056e13f60 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -46,6 +46,14 @@ struct gpio_irq_chip { */ const struct irq_domain_ops *domain_ops; + /** + * @first: + * + * If not dynamically assigned, the base (first) IRQ to allocate GPIO + * chip IRQs from (deprecated). + */ + unsigned int first; + /** * @parent_handler: * @@ -130,7 +138,6 @@ static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip) * safely. * @bgpio_dir: shadowed direction register for generic GPIO to clear/set * direction safely. - * @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated) * @irq_handler: the irq handler to use (often a predefined irq core function) * for GPIO IRQs, provided by GPIO driver * @irq_default_type: default IRQ triggering type applied during GPIO driver @@ -210,7 +217,6 @@ struct gpio_chip { * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib * to handle IRQs for most practical cases. */ - unsigned int irq_base; irq_flow_handler_t irq_handler; unsigned int irq_default_type; unsigned int irq_chained_parent;