From patchwork Tue Nov 15 16:04:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 695101 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tJC090g41z9t2C for ; Wed, 16 Nov 2016 03:05:13 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LPxHIaJR"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751762AbcKOQFM (ORCPT ); Tue, 15 Nov 2016 11:05:12 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:36179 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752275AbcKOQFL (ORCPT ); Tue, 15 Nov 2016 11:05:11 -0500 Received: by mail-pf0-f195.google.com with SMTP id c4so5648688pfb.3 for ; Tue, 15 Nov 2016 08:05:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=y+XOtWqbrLQ23xQzrBHVeGoG8hRsBTm8S7g3ZxDBFWs=; b=LPxHIaJRgK/mikhVyiQZG3s6PX/dwr61QFWeT5Js94upczdPrJjLfgfjJk1ax/+BdD z04pPFzdF0908s+Z4UfJtC5GkRBDmz0aANMPmv+T5/dF82cCwnLk4kJmkSnlOQmE3o1E mDG3iE34FtYGZFXn71ex2Oe9HavRGPD7R8uLEwuqGoMwgL1RqL4G05GdXRKai9vpAY9q +o6HzXLqpTuU0JJja3NipgSmSW+qri1vALRZctuf7uG67NfOb5p9UFf6LoL11+HWyx2c 11ExmfqsXVTiAbQ+TfhRkhkUiHposvJDRSgswIp+uOlYR1p5tPSB8oGb7gqHruZqL1ct 6dXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=y+XOtWqbrLQ23xQzrBHVeGoG8hRsBTm8S7g3ZxDBFWs=; b=AMXHOjouXEQNLy4NXH9LMoRpwR1eQ0etCQsXqqNSe90Ij3iRy9/csrSVOxi08X47xW Wxj6KbI40pe/ACk496TOeVbR6vgoNYOfBepwweUmihVnRPZQ87BwjjnZafFFE0/NFdRn HQe14DdqQUYR+okU3UZkKcoE4u0jJ1BtYGCCaXGZ0XnD2guK00H6mFOohZlLQOgGwgP/ aij+vWgRQpcNFDDUkzE0HSLg366nc53Y/pgXkHjz5TlWlzCYTl2CGY0UihNnqBrBh2Dv BRo1p3b+fUPtzn/OoB9Ono3FyYbNiik+8qmpm8krAvIosM6SdcofYF0/eOPWIzLrEZYR 3ATQ== X-Gm-Message-State: ABUngvfAhqyUhUaYggTEw/KwQhyU8Z7tnOc4kZuxZ01D6Abu0DkH+oop+uNabvf86AMmbg== X-Received: by 10.98.213.7 with SMTP id d7mr47852097pfg.3.1479225910471; Tue, 15 Nov 2016 08:05:10 -0800 (PST) Received: from localhost (port-11995.pppoe.wtnet.de. [84.46.47.10]) by smtp.gmail.com with ESMTPSA id q27sm18799569pfd.49.2016.11.15.08.05.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 Nov 2016 08:05:09 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Stephen Warren , Alexandre Courbot , Jon Hunter , Joseph Lo , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 4/5] dt-bindings: Add power domains to Tegra BPMP firmware Date: Tue, 15 Nov 2016 17:04:51 +0100 Message-Id: <20161115160452.27183-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161115160452.27183-1-thierry.reding@gmail.com> References: <20161115160452.27183-1-thierry.reding@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Stephen Warren The Tegra186 BPMP is also a provider of power domains. Enhance the device tree binding to describe this. Signed-off-by: Stephen Warren Acked-by: Rob Herring Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../bindings/firmware/nvidia,tegra186-bpmp.txt | 10 ++++-- include/dt-bindings/power/tegra186-powergate.h | 39 ++++++++++++++++++++++ 2 files changed, 46 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/power/tegra186-powergate.h diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt index 7c7edaf1cd62..0d3fef423c48 100644 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt @@ -17,6 +17,7 @@ Required properties: - shmem : List of the phandle of the TX and RX shared memory area that the IPC between CPU and BPMP is based on. - #clock-cells : Should be 1. +- #power-domain-cells : Should be 1. - #reset-cells : Should be 1. This node is a mailbox consumer. See the following files for details of @@ -26,12 +27,14 @@ provider(s): - .../mailbox/mailbox.txt - .../mailbox/nvidia,tegra186-hsp.txt -This node is a clock and reset provider. See the following files for -general documentation of those features, and the specifiers implemented -by this node: +This node is a clock, power domain, and reset provider. See the following +files for general documentation of those features, and the specifiers +implemented by this node: - .../clock/clock-bindings.txt - +- ../power/power_domain.txt +- - .../reset/reset.txt - @@ -77,5 +80,6 @@ bpmp { mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; }; diff --git a/include/dt-bindings/power/tegra186-powergate.h b/include/dt-bindings/power/tegra186-powergate.h new file mode 100644 index 000000000000..388d6e228dc8 --- /dev/null +++ b/include/dt-bindings/power/tegra186-powergate.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H +#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H + +#define TEGRA186_POWER_DOMAIN_AUD 0 +#define TEGRA186_POWER_DOMAIN_DFD 1 +#define TEGRA186_POWER_DOMAIN_DISP 2 +#define TEGRA186_POWER_DOMAIN_DISPB 3 +#define TEGRA186_POWER_DOMAIN_DISPC 4 +#define TEGRA186_POWER_DOMAIN_ISPA 5 +#define TEGRA186_POWER_DOMAIN_NVDEC 6 +#define TEGRA186_POWER_DOMAIN_NVJPG 7 +#define TEGRA186_POWER_DOMAIN_MPE 8 +#define TEGRA186_POWER_DOMAIN_PCX 9 +#define TEGRA186_POWER_DOMAIN_SAX 10 +#define TEGRA186_POWER_DOMAIN_VE 11 +#define TEGRA186_POWER_DOMAIN_VIC 12 +#define TEGRA186_POWER_DOMAIN_XUSBA 13 +#define TEGRA186_POWER_DOMAIN_XUSBB 14 +#define TEGRA186_POWER_DOMAIN_XUSBC 15 +#define TEGRA186_POWER_DOMAIN_GPU 43 +#define TEGRA186_POWER_DOMAIN_MAX 44 + +#endif