From patchwork Thu Jun 23 10:27:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 639572 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rZyN91jvjz9sxS for ; Thu, 23 Jun 2016 20:28:09 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=h5X6UgPS; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751670AbcFWK2H (ORCPT ); Thu, 23 Jun 2016 06:28:07 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34570 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751549AbcFWK2F (ORCPT ); Thu, 23 Jun 2016 06:28:05 -0400 Received: by mail-pf0-f195.google.com with SMTP id 66so6484812pfy.1; Thu, 23 Jun 2016 03:28:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=3hN7GK3w75wnboygUFLCrVAlXXfUMb9TWrcd3KsGx1E=; b=h5X6UgPS5W7wZgotrNRzGej1KQKSpthRnW0qp0WU4+Bbvwfzcx8BUIJwqleqlwZHti kjXG+bFw/wEO1k92FDYMRCTJuqVYJVI+MmSC53zMHgdemiLrRVtqeX2tvLGBoVWmUlza roPOQGwahprSpzyEZxkBWtuBUDMD4N7uC5uF22oF9I+QdCDxZS7txSiaMJoDEYgWy10P 43rge4gE7GTSIkTGv6QSHTZE3G90MRL++d7ALHDzvs9x1kdUi7f21BnNC/7ZTMfphr8c 2YKHT+74Zz5WIcbNHYTEu1t3hzBe2e/XMjXa1PPCs2z3oYN+cq/6+7yX5OaxpLNLg30E AY4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=3hN7GK3w75wnboygUFLCrVAlXXfUMb9TWrcd3KsGx1E=; b=U0fMkPkmUMtUre4wqOZlH2CjBvzMwtIjZUbAOgS4O8MvAkZRuqDD5VhYrO8Z77cS45 KrIJMn0adMzLWDHL+Wl7GddroDv50QtqXgcQNVV4KhTmUAfK8iJqo2wFlSoFxvebMQYN MfRrzBugx3fcXnvaAyBpp/2saZp6onne3UNUH2yNyXRBWg1NDaGwObFU4By+jOQpBawf iWc2akjSakt5wwElF/cx12xWFtdhNRA66jIouPOB9U1BeAm5M3BdAaJdkeJqdRgX9Oz5 x9hMOjbGzVI3ZsOov1+632dE3HD+4mukizc97wSaqwaV5iVyOw/Zagbhr0EFlBphCWOP Ajbg== X-Gm-Message-State: ALyK8tJc03VqEMVK+rb33+0T5lygq+aCl3uw2/PCbMqj8X8ChkBasuIfDzDOmNRKK3A+Rg== X-Received: by 10.98.152.76 with SMTP id q73mr42082909pfd.38.1466677684517; Thu, 23 Jun 2016 03:28:04 -0700 (PDT) Received: from localhost (port-20003.pppoe.wtnet.de. [46.59.139.199]) by smtp.gmail.com with ESMTPSA id k22sm6215415pfj.16.2016.06.23.03.28.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Jun 2016 03:28:03 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: display: tegra: Add source clock for SOR Date: Thu, 23 Jun 2016 12:27:58 +0200 Message-Id: <20160623102759.23078-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.8.3 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The SOR clock can have various sources, with the most commonly used being the sor_safe, pll_d2_out0, pll_dp and sor_brick clocks. These are configured using a three level mux, of which the first 2 levels can be treated as one. The direct parents of the SOR clock are the sor_safe, sor_brick and sor_src clocks, whereas the pll_d2_out0 and pll_dp clocks can be selected as parents of the sor_src clock via a second mux. Previous generations of Tegra have only supported eDP and LVDS with the SOR, where LVDS was never used on publicly available hardware. Clocking for this only ever required the first level mux (to select between sor_safe and sor_brick). Tegra210 has a new revision of the SOR that supports HDMI and hence needs to support the second level mux to allow selecting pll_d2_out0 as the SOR clock's parent. This second mux is knows as sor_src, and operating system software needs a reference to it in order to select the proper parent. Signed-off-by: Thierry Reding --- .../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index a3bd8c050c4e..21de27a7f0a1 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -208,6 +208,7 @@ of the following host1x client modules: See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - sor: clock input for the SOR hardware + - source: source clock for the SOR clock - parent: input for the pixel clock - dp: reference clock for the SOR clock - safe: safe reference for the SOR clock during power up