From patchwork Tue Jun 21 15:30:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 638752 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rYsDM3kSsz9sR8 for ; Wed, 22 Jun 2016 01:32:35 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=pg2y1w9r; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751799AbcFUPca (ORCPT ); Tue, 21 Jun 2016 11:32:30 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:34125 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751380AbcFUPbA (ORCPT ); Tue, 21 Jun 2016 11:31:00 -0400 Received: by mail-pf0-f194.google.com with SMTP id 66so1594116pfy.1; Tue, 21 Jun 2016 08:30:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=vf+cAdZO/Lw4LfEogJht3HvPvrth23QtzDWdUCkA2Qg=; b=pg2y1w9rqPTE2mxwq40/fqKCGY0TatLt0gjXu/aH5Vs813V3OUxKySBdq4Z0JxAylb aOpPfHA2uNfhoeGOmlW0LLz4kz/lSJmM75j1pFLdsDpMf1F4GV5qfvCsNpzDd4Uok6x6 UUXHUEBgrA+ef8FZJ5v/xwK9EB63SzckuYj1AIFd1nUaXkyTzBtWhxnWmFzsMy/Bae2g pmvHXBOyXVL7kGx4ynX+YzSuXm9CTNajjqzPrm0MjEaver3ONP2hh4Pcpt/u5w6uh7cY 8zCAo7G1M0gN4hJpdYatFjeq/BXxAu6p5XpFS6QvqMWgTAlPiuQSCO1O3pqKQCDySdGR 8h7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=vf+cAdZO/Lw4LfEogJht3HvPvrth23QtzDWdUCkA2Qg=; b=MRPEK5c8skfmhJiq/ZxE0+y88TtSYrpQMJfpIL/Euwk2tBuMrg9lzmQ2MHYaZaSsjc CuxNjPEfMC90yQzo0oKup9Y51HFaoK/RaRND6oru9acoDztpq70RPU1zIoRuj+6JmY03 ugofQBI1I+aumuvUyfDg4/DNY0037XkFtGVE/sDeLLbCLC/txBNfCvSI29ax+3SPZ8zu m4IGqBnY9jtiszUe/jZbPMCf9+1mKuVcGJP3eomNImNPa+V8S9jI5/OI5+6176Fex5lA ZqBuzUNZGXbsZW9fH89te8r2qi1EM9aubdFmDBUtN+JeTnvwr9C1Q4Wmi8er24UAl7HU +m6w== X-Gm-Message-State: ALyK8tLePh1u/iWjr8H9dZWyelvvQ1CkZ/io+4NcfVlpVGejApCDpKjsJuw8CjMoaI0sAQ== X-Received: by 10.98.75.83 with SMTP id y80mr28565387pfa.97.1466523039153; Tue, 21 Jun 2016 08:30:39 -0700 (PDT) Received: from localhost (port-34725.pppoe.wtnet.de. [46.59.186.126]) by smtp.gmail.com with ESMTPSA id b71sm64459037pfc.51.2016.06.21.08.30.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Jun 2016 08:30:38 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Alexandre Courbot , Rhyland Klein , Jon Hunter , Peter De Schrijver , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH] clk: tegra: Mark timer clock as critical Date: Tue, 21 Jun 2016 17:30:35 +0200 Message-Id: <20160621153035.22172-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.8.3 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The timer clock feeds the timer block, which, among other things, is used to drive the SOR lane sequencer. Since the Tegra timer driver is not enabled on 64-bit ARM, nothing currently claims that clock and it gets disabled by the common clock framework at late_init time. Given the non-obvious dependencies, the timer clock can be considered a critical part of the SoC infrastructure, requiring its clock source to be always on. Signed-off-by: Thierry Reding Acked-by: Rhyland Klein Acked-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra-periph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index af85c8aeaf5a..4ce4e7fb1124 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -792,7 +792,7 @@ static struct tegra_periph_init_data periph_clks[] = { static struct tegra_periph_init_data gate_clks[] = { GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), - GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0), + GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL), GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),