From patchwork Tue Jun 14 12:00:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 635215 X-Patchwork-Delegate: treding@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rTSsK1lfcz9t1B for ; Tue, 14 Jun 2016 22:00:53 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=X+8sJU6u; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751624AbcFNMAw (ORCPT ); Tue, 14 Jun 2016 08:00:52 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:36603 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751226AbcFNMAw (ORCPT ); Tue, 14 Jun 2016 08:00:52 -0400 Received: by mail-wm0-f65.google.com with SMTP id m124so21811380wme.3; Tue, 14 Jun 2016 05:00:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=x+F+RPoX3rdzlJZfEoIPdFOVhVdfpAdWhbMmyOg2a8g=; b=X+8sJU6us/Nbas7xrtsamgpSyLlJfYFIFt3v0IswdqR0Ee0xkeMtHTctXXxAcZTJFY 0fj+EAHiIDDsqRbqSKLq26bPykD8abT2t5/whcUYGXuj1gMTBbfeY/9Dp3ZsI6VwYBgB tNrlVXpAmAvVL95md4VypUR1vITvvza6p0tQTmBNcrCD9/mkcZHIFh3al7DELoa2ZUO7 Ku19IsBxez9gNvahp8zpQeT7V14+XWv5V+U5TWqh4HsyGC3K+Ov3avzruTdESabQHP4q 4U7wqEmdT9srRIutWgA5DOLsf337rsEad8MYVIU+gArvg3bUnzs8jzoXcEGi+1TsNpAE blsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=x+F+RPoX3rdzlJZfEoIPdFOVhVdfpAdWhbMmyOg2a8g=; b=bcadvc3t8APwHvy42d57T1tyJo/rbANMXiCAJSPaaBOsDgh0pYeM1wWPvlwe1Whvt9 8c5IPx5lfdYD2ouIrAVqF+PCuAITaxJRwF+Epmn6VdmcMoDaMQ24ftxO/bnfpD3JVmq/ rt9nVy2JIWeHgsuVUmPvf2/hLJQjILPV1SCRmT+otjangkIZdJvkFl7GXwytq/9+sCGj 39XYtPsEiK5aYkCUyOZ7PSkWlH0fjHLj1YrYevi5J2HoH18XRenqMj6fwjmVtSE5QFIG IhHxlHWLn7X9H04LeieP9VGLFrG1Vqo/qO02++NT2qtrAMkwBjybLy81xHSYBPmZt7KB WR9A== X-Gm-Message-State: ALyK8tK3T50nmvHjeoUa55cubYzzoSZW97e0PgBOy52s41q4dgDqJFrOYzLBZhNsfLXQ3g== X-Received: by 10.28.145.203 with SMTP id t194mr6249993wmd.88.1465905650525; Tue, 14 Jun 2016 05:00:50 -0700 (PDT) Received: from localhost (port-11930.pppoe.wtnet.de. [84.46.46.200]) by smtp.gmail.com with ESMTPSA id w76sm3794656wmd.11.2016.06.14.05.00.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Jun 2016 05:00:49 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Peter De Schrijver , Alexandre Courbot , Rhyland Klein , Jon Hunter , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 3/3] clk: tegra: Enable sor1 and sor1_src on Tegra210 Date: Tue, 14 Jun 2016 14:00:44 +0200 Message-Id: <20160614120044.30734-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160614120044.30734-1-thierry.reding@gmail.com> References: <20160614120044.30734-1-thierry.reding@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Make the sor1 and sor1_src clocks available on Tegra210. They will be used by the display driver to support HDMI and DP. Signed-off-by: Thierry Reding Acked-by: Peter De Schrijver Acked-by: Rhyland Klein --- drivers/clk/tegra/clk-tegra210.c | 2 ++ include/dt-bindings/clock/tegra210-car.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index cd141a364c9d..8e37eda37449 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2093,6 +2093,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true }, [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true }, [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true }, + [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true }, + [tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true }, [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true }, [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, }, [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true }, diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index bd3530e56d46..35288b20f2c9 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -308,7 +308,7 @@ #define TEGRA210_CLK_CLK_OUT_3 279 #define TEGRA210_CLK_BLINK 280 /* 281 */ -/* 282 */ +#define TEGRA210_CLK_SOR1_SRC 282 /* 283 */ #define TEGRA210_CLK_XUSB_HOST_SRC 284 #define TEGRA210_CLK_XUSB_FALCON_SRC 285