From patchwork Tue Jun 14 12:00:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 635213 X-Patchwork-Delegate: treding@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rTSsG0HkMz9t1B for ; Tue, 14 Jun 2016 22:00:50 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=xr7aatTd; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751179AbcFNMAs (ORCPT ); Tue, 14 Jun 2016 08:00:48 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:34330 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751140AbcFNMAs (ORCPT ); Tue, 14 Jun 2016 08:00:48 -0400 Received: by mail-wm0-f66.google.com with SMTP id n184so21876184wmn.1; Tue, 14 Jun 2016 05:00:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=Vl2mmEep1WfGIYsmHG6KboVVeGKyOZ1OjmrETcJ+yOY=; b=xr7aatTddYMTk+OWHJWabm7jVIv+Ddq3gqq+QNwAuJA0Eh3JJwp16j9HnN5Qm1vOc4 sW6HHnvDqOqGrNp+Lpu586KvaBXttA0AF68HqCZV0kpblEApoQI+gfGkjDizRdLs7O1A AwpSlYnxexxtT2/MQ2qaeZGaBLIlCOP6Kf11nDijVVFaHVkfi86UwTKwkLYVWNgphFlo MKJMUg8YxoLdMGotA2JZhKsvCZt+XL80NTkpMqIJT4AcGJJqMhotWjuBwVtLjw0q++x+ ThV7Jik+/yalIq0exBHi5COiHLfb2tvDMMEs+27QWg+K36U8ANKBYuO5ATj5gICjMeYl zB0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Vl2mmEep1WfGIYsmHG6KboVVeGKyOZ1OjmrETcJ+yOY=; b=mQWWon5giFYp/273Da6tNI7+3EuvfLq4fW+hvUMGEKIXM96MWM6+RU6rQpcd2GLr6B h2siuWnxw7cGdy9o+kjXbZjcx27wPWGVT+k6MylbMbncQ9ygTD511MUq0Gy9MPg/1ht2 H7QmwU7fsr3vUolP/WVYHPi6drA6kVJVa8BoqueBCqMZWP+O58lmS21B2ri1MdZ3ciWy NQiuy+nsOfMA1SLJQ/RehW9yeRWCofIzfUw0YzfknYVdS0WuzSh4+HsWuFq4KGqdMpwA QvFATM8i8TYtSDWMEYJZMigjPKxwPT0ReIqt+hlorF3MVkRGK8j4RmiNYqpuGcUlLp3U 5yaw== X-Gm-Message-State: ALyK8tLLNHkbqJsLV7bi07pCs3ulMCrsgILAdzQQ2zfFpIgmXvi4VCcKK6Gn3KnOW4rDlg== X-Received: by 10.194.83.202 with SMTP id s10mr5858231wjy.17.1465905646401; Tue, 14 Jun 2016 05:00:46 -0700 (PDT) Received: from localhost (port-11930.pppoe.wtnet.de. [84.46.46.200]) by smtp.gmail.com with ESMTPSA id r16sm3778648wmb.23.2016.06.14.05.00.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Jun 2016 05:00:45 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Peter De Schrijver , Alexandre Courbot , Rhyland Klein , Jon Hunter , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 1/3] clk: tegra: Disable spread spectrum on pll_d2 Date: Tue, 14 Jun 2016 14:00:42 +0200 Message-Id: <20160614120044.30734-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.8.3 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Enabling spread spectrum on pll_d2 can lead to issues with display modes. HDMI monitors, for example, would report "Signal Error" and some modes driven over DisplayPort would generate fuzzy horizontal bands. Signed-off-by: Thierry Reding Acked-by: Peter De Schrijver Acked-by: Rhyland Klein --- drivers/clk/tegra/clk-tegra210.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 6bd1235d09b1..cd141a364c9d 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -1914,8 +1914,9 @@ static struct tegra_clk_pll_params pll_d2_params = { .sdm_din_mask = PLLA_SDM_DIN_MASK, .sdm_ctrl_reg = PLLD2_MISC1, .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK, - .ssc_ctrl_reg = PLLD2_MISC1, - .ssc_ctrl_en_mask = PLLD2_SSC_EN_MASK, + /* disable spread-spectrum for pll_d2 */ + .ssc_ctrl_reg = 0, + .ssc_ctrl_en_mask = 0, .round_p_to_pdiv = pll_qlin_p_to_pdiv, .pdiv_tohw = pll_qlin_pdiv_to_hw, .div_nmp = &pllss_nmp,