From patchwork Thu May 26 15:40:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 626753 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rFtg56RR2z9t62 for ; Fri, 27 May 2016 01:41:53 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=wR5hQJx9; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754437AbcEZPkQ (ORCPT ); Thu, 26 May 2016 11:40:16 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34502 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754432AbcEZPkN (ORCPT ); Thu, 26 May 2016 11:40:13 -0400 Received: by mail-pf0-f195.google.com with SMTP id c84so2332302pfc.1; Thu, 26 May 2016 08:40:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q+pRY20hbhQUocwUhP4npqSN3GGo3kb98TVti9ty5RM=; b=wR5hQJx9Aw9owHrJyy1z4yf1UShLF6fpW3MjQyKeDMH0+l+SU18cPguySmM95f5ypt URrUSYWDyfjf8FZ96NsoZdklRUw3pq+WP4e22Gwe39ZvghDDbsBA8BbAIRVLd1Kt/Lza cwLQXp8pxRKNgngvu01wY1ayp+VIVfmu1q2546cT7dUv9sbS0gEaPs3x+h2En6p5jVjd 8hGLWtwaHbCdfNPyXizMNlYT89/akgJHOu5wVfftJiF2esEUAYoJW+82T7rGWAbsR2nS DPtjkMTt33KSPtPzDu/17h+TR4vAWHlYxhf5IENeTEp2NST/a4heLFkOX51/WDC9MMCF Qn1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q+pRY20hbhQUocwUhP4npqSN3GGo3kb98TVti9ty5RM=; b=VWcCtTjheOBB0MKF2n2AfxL4aq3IjyskIMWM4tq0k9qSP2rtBo2Vf2kMxrFTWdsG5Q a2jaTwjkObACIk5uY0L2iDDFyOodiEFoQaS/skHumqPGuYgXR1f5U6EcTgqSy8f0Dnxp z+jxDuov81QuzUGEqY7bHu2hJBxjvzHJcQT2WsSUyLLGvAxQ9cGO9GVGuhdNWwStSTNd ql3uWGvxUAt4zpTiSMRJWX6cr1gXTIto4ZeL/4LfzObCOr+ZDvrn7r1EkFI85Ya/LVLW PR0fGFP5hVaAVZ0fNoBRrQ9Dfan0rtcyX9HhLWLBeTlFlioM05pG001rT3BKu4L2H6iH EP1Q== X-Gm-Message-State: ALyK8tLtwQL5y/vJ+lDzbe8A6TnLdHINGtUo9GUn3dNPo+fqqBvkdRPh0T0/TpOgfQV5BA== X-Received: by 10.98.36.140 with SMTP id k12mr15042300pfk.118.1464277212923; Thu, 26 May 2016 08:40:12 -0700 (PDT) Received: from localhost (port-54928.pppoe.wtnet.de. [46.59.215.64]) by smtp.gmail.com with ESMTPSA id qm10sm21394248pac.33.2016.05.26.08.40.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 May 2016 08:40:11 -0700 (PDT) From: Thierry Reding To: Peter Chen , Greg Kroah-Hartman Cc: Stephen Warren , Thierry Reding , Alexandre Courbot , Jon Hunter , linux-usb@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC 1/5] usb: chipidea: Add support for Tegra20/30/114/124 Date: Thu, 26 May 2016 17:40:01 +0200 Message-Id: <20160526154005.11558-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160526154005.11558-1-thierry.reding@gmail.com> References: <20160526154005.11558-1-thierry.reding@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding All of these Tegra SoC generations have a ChipIdea UDC IP block that can be used for device mode communication with a host. Implement rudimentary support that doesn't allow switching between host and device modes. Signed-off-by: Thierry Reding --- drivers/usb/chipidea/Makefile | 1 + drivers/usb/chipidea/ci_hdrc_tegra.c | 109 +++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 drivers/usb/chipidea/ci_hdrc_tegra.c diff --git a/drivers/usb/chipidea/Makefile b/drivers/usb/chipidea/Makefile index 518e445476c3..3532df6561d9 100644 --- a/drivers/usb/chipidea/Makefile +++ b/drivers/usb/chipidea/Makefile @@ -10,6 +10,7 @@ ci_hdrc-$(CONFIG_USB_OTG_FSM) += otg_fsm.o obj-$(CONFIG_USB_CHIPIDEA) += ci_hdrc_usb2.o obj-$(CONFIG_USB_CHIPIDEA) += ci_hdrc_msm.o obj-$(CONFIG_USB_CHIPIDEA) += ci_hdrc_zevio.o +obj-$(CONFIG_USB_CHIPIDEA) += ci_hdrc_tegra.o obj-$(CONFIG_USB_CHIPIDEA_PCI) += ci_hdrc_pci.o diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c new file mode 100644 index 000000000000..d3cd68441856 --- /dev/null +++ b/drivers/usb/chipidea/ci_hdrc_tegra.c @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2016, NVIDIA Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include + +#include "ci.h" + +struct tegra_udc { + struct ci_hdrc_platform_data data; + struct platform_device *dev; + + struct usb_phy *phy; + struct clk *clk; +}; + +static const struct of_device_id tegra_udc_of_match[] = { + { .compatible = "nvidia,tegra20-udc" }, + { .compatible = "nvidia,tegra30-udc" }, + { .compatible = "nvidia,tegra114-udc" }, + { .compatible = "nvidia,tegra124-udc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, tegra_udc_of_match); + +static int tegra_udc_probe(struct platform_device *pdev) +{ + struct tegra_udc *udc; + int err; + + udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL); + if (!udc) + return -ENOMEM; + + udc->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0); + if (IS_ERR(udc->phy)) { + err = PTR_ERR(udc->phy); + dev_err(&pdev->dev, "failed to get PHY: %d\n", err); + return err; + } + + udc->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(udc->clk)) { + err = PTR_ERR(udc->clk); + dev_err(&pdev->dev, "failed to get clock: %d\n", err); + return err; + } + + err = clk_prepare_enable(udc->clk); + if (err < 0) { + dev_err(&pdev->dev, "failed to enable clock: %d\n", err); + return err; + } + + /* setup and register ChipIdea HDRC device */ + udc->data.name = "tegra-udc"; + udc->data.capoffset = DEF_CAPOFFSET; + udc->data.flags = 0; + udc->data.usb_phy = udc->phy; + + udc->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource, + pdev->num_resources, &udc->data); + if (IS_ERR(udc->dev)) { + err = PTR_ERR(udc->dev); + dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err); + goto disable_clock; + } + + platform_set_drvdata(pdev, udc); + + return 0; + +disable_clock: + clk_disable_unprepare(udc->clk); + return err; +} + +static int tegra_udc_remove(struct platform_device *pdev) +{ + struct tegra_udc *udc = platform_get_drvdata(pdev); + + clk_disable_unprepare(udc->clk); + + return 0; +} + +static struct platform_driver tegra_udc_driver = { + .driver = { + .name = "tegra-udc", + .of_match_table = tegra_udc_of_match, + }, + .probe = tegra_udc_probe, + .remove = tegra_udc_remove, +}; +module_platform_driver(tegra_udc_driver); + +MODULE_DESCRIPTION("NVIDIA Tegra USB device mode driver"); +MODULE_AUTHOR("Thierry Reding "); +MODULE_ALIAS("platform:tegra-udc"); +MODULE_LICENSE("GPL v2");