| Message ID | 1635427419-22478-2-git-send-email-akhilrajeev@nvidia.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add NVIDIA Tegra GPC-DMA driver | expand |
On Thu, Oct 28, 2021 at 06:53:36PM +0530, Akhil R wrote: > Add DT binding document for Nvidia Tegra GPCDMA controller. > > Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com> > Signed-off-by: Akhil R <akhilrajeev@nvidia.com> > Reviewed-by: Jon Hunter <jonathanh@nvidia.com> > --- > .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 115 +++++++++++++++++++++ > 1 file changed, 115 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > > diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > new file mode 100644 > index 0000000..bc97efc > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > @@ -0,0 +1,115 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings > + > +description: | > + The Tegra General Purpose Central (GPC) DMA controller is used for faster > + data transfers between memory to memory, memory to device and device to > + memory. > + > +maintainers: > + - Jon Hunter <jonathanh@nvidia.com> > + - Rajesh Gumasta <rgumasta@nvidia.com> > + > +allOf: > + - $ref: "dma-controller.yaml#" > + > +properties: > + compatible: > + oneOf: > + - enum: > + - nvidia,tegra186-gpcdma > + - nvidia,tegra194-gpcdma > + - items: > + - const: nvidia,tegra186-gpcdma > + - const: nvidia,tegra194-gpcdma One of these is wrong. Either 186 has a fallback to 194 or it doesn't. > + > + "#dma-cells": > + const: 1 > + > + reg: > + maxItems: 1 > + > + interrupts: > + description: | Don't need '|' if there's no formatting. > + Should contain all of the per-channel DMA interrupts in > + ascending order with respect to the DMA channel index. > + minItems: 1 > + maxItems: 32 > + > + resets: > + description: | > + Should contain the reset phandle for gpcdma. Not really a useful description. Drop. > + maxItems: 1 > + > + reset-names: > + const: gpcdma > + > + iommus: > + maxItems: 1 > + > + dma-coherent: true > + > +required: > + - compatible > + - reg > + - interrupts > + - resets > + - reset-names > + - "#dma-cells" > + - iommus > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/memory/tegra186-mc.h> > + #include <dt-bindings/reset/tegra186-reset.h> > + > + dma-controller@2600000 { > + compatible = "nvidia,tegra186-gpcdma"; > + reg = <0x2600000 0x0>; > + resets = <&bpmp TEGRA186_RESET_GPCDMA>; > + reset-names = "gpcdma"; > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; > + dma-coherent; > + }; > +... > -- > 2.7.4 > >
> On Thu, Oct 28, 2021 at 06:53:36PM +0530, Akhil R wrote: > > Add DT binding document for Nvidia Tegra GPCDMA controller. > > > > Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com> > > Signed-off-by: Akhil R <akhilrajeev@nvidia.com> > > Reviewed-by: Jon Hunter <jonathanh@nvidia.com> > > --- > > .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 115 > +++++++++++++++++++++ > > 1 file changed, 115 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > > b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > > new file mode 100644 > > index 0000000..bc97efc > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.ya > > +++ ml > > @@ -0,0 +1,115 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings > > + > > +description: | > > + The Tegra General Purpose Central (GPC) DMA controller is used for > > +faster > > + data transfers between memory to memory, memory to device and > > +device to > > + memory. > > + > > +maintainers: > > + - Jon Hunter <jonathanh@nvidia.com> > > + - Rajesh Gumasta <rgumasta@nvidia.com> > > + > > +allOf: > > + - $ref: "dma-controller.yaml#" > > + > > +properties: > > + compatible: > > + oneOf: > > + - enum: > > + - nvidia,tegra186-gpcdma > > + - nvidia,tegra194-gpcdma > > + - items: > > + - const: nvidia,tegra186-gpcdma > > + - const: nvidia,tegra194-gpcdma > > One of these is wrong. Either 186 has a fallback to 194 or it doesn't. Not sure if I understood this correctly. Tegra186 and 194 have different chip data inside driver based on the compatible. I guess, it then needs to be one of these. Or is the mistake something related to formatting? Agreed with other comments. -- nvpublic
On Wed, Nov 3, 2021 at 5:34 AM Akhil R <akhilrajeev@nvidia.com> wrote: > > > On Thu, Oct 28, 2021 at 06:53:36PM +0530, Akhil R wrote: > > > Add DT binding document for Nvidia Tegra GPCDMA controller. > > > > > > Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com> > > > Signed-off-by: Akhil R <akhilrajeev@nvidia.com> > > > Reviewed-by: Jon Hunter <jonathanh@nvidia.com> > > > --- > > > .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 115 > > +++++++++++++++++++++ > > > 1 file changed, 115 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > > > b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml > > > new file mode 100644 > > > index 0000000..bc97efc > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.ya > > > +++ ml > > > @@ -0,0 +1,115 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings > > > + > > > +description: | > > > + The Tegra General Purpose Central (GPC) DMA controller is used for > > > +faster > > > + data transfers between memory to memory, memory to device and > > > +device to > > > + memory. > > > + > > > +maintainers: > > > + - Jon Hunter <jonathanh@nvidia.com> > > > + - Rajesh Gumasta <rgumasta@nvidia.com> > > > + > > > +allOf: > > > + - $ref: "dma-controller.yaml#" > > > + > > > +properties: > > > + compatible: > > > + oneOf: > > > + - enum: > > > + - nvidia,tegra186-gpcdma > > > + - nvidia,tegra194-gpcdma > > > + - items: > > > + - const: nvidia,tegra186-gpcdma > > > + - const: nvidia,tegra194-gpcdma > > > > One of these is wrong. Either 186 has a fallback to 194 or it doesn't. > Not sure if I understood this correctly. Tegra186 and 194 have different chip data > inside driver based on the compatible. I guess, it then needs to be one of these. > Or is the mistake something related to formatting? It's not about what the driver uses, but what is valid in a DT file. Either you say the 2 implementations are different and in no way compatible with each other: enum: - nvidia,tegra186-gpcdma - nvidia,tegra194-gpcdma Or you say 186 is backwards compatible with 194 (meaning 186 is a superset of 194 so a driver written for 194 still works on 186 (though not any new features)). oneOf: - const: nvidia,tegra194-gpcdma - items: - const: nvidia,tegra186-gpcdma - const: nvidia,tegra194-gpcdma Rob
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml new file mode 100644 index 0000000..bc97efc --- /dev/null +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings + +description: | + The Tegra General Purpose Central (GPC) DMA controller is used for faster + data transfers between memory to memory, memory to device and device to + memory. + +maintainers: + - Jon Hunter <jonathanh@nvidia.com> + - Rajesh Gumasta <rgumasta@nvidia.com> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra186-gpcdma + - nvidia,tegra194-gpcdma + - items: + - const: nvidia,tegra186-gpcdma + - const: nvidia,tegra194-gpcdma + + "#dma-cells": + const: 1 + + reg: + maxItems: 1 + + interrupts: + description: | + Should contain all of the per-channel DMA interrupts in + ascending order with respect to the DMA channel index. + minItems: 1 + maxItems: 32 + + resets: + description: | + Should contain the reset phandle for gpcdma. + maxItems: 1 + + reset-names: + const: gpcdma + + iommus: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - resets + - reset-names + - "#dma-cells" + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/tegra186-mc.h> + #include <dt-bindings/reset/tegra186-reset.h> + + dma-controller@2600000 { + compatible = "nvidia,tegra186-gpcdma"; + reg = <0x2600000 0x0>; + resets = <&bpmp TEGRA186_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + }; +...