From patchwork Mon Jul 20 06:34:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajesh Gumasta X-Patchwork-Id: 1332057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=DBt1PS1f; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4B9BmG14tYz9sRN for ; Mon, 20 Jul 2020 16:34:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727121AbgGTGeu (ORCPT ); Mon, 20 Jul 2020 02:34:50 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:18520 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727115AbgGTGet (ORCPT ); Mon, 20 Jul 2020 02:34:49 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 19 Jul 2020 23:34:35 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 19 Jul 2020 23:34:48 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 19 Jul 2020 23:34:48 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 20 Jul 2020 06:34:43 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 20 Jul 2020 06:34:43 +0000 Received: from rgumasta-linux.nvidia.com (Not Verified[10.19.66.108]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sun, 19 Jul 2020 23:34:43 -0700 From: Rajesh Gumasta To: , , , , , , , , CC: , Subject: [Patch v1 4/4] arm64: tegra: Add GPCDMA node in dt Date: Mon, 20 Jul 2020 12:04:16 +0530 Message-ID: <1595226856-19241-5-git-send-email-rgumasta@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595226856-19241-1-git-send-email-rgumasta@nvidia.com> References: <1595226856-19241-1-git-send-email-rgumasta@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595226875; bh=tc/XzjGQyzMqGlRhGZ2uP3xW0f0gkcCZd8iJhKBcbso=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=DBt1PS1fQt2dZ2ukyVKd1eVcRXK90yZ5a7LPApGRLTAQ+/wsGyvWgDt5RmQQq4aMI Ml+YpBj/cLUMXUERKWaOq6ZtUDmzVIB2LVqJr4rXa3hHd3k8aVreYX0rmv/huABrRR SI6vf0UXznGbl/RcGZ+BDGjaTEzGdnomEl655wtfy9f7v52c0Lt6lxLcOonjA5PFh9 MXY+hU7gxsWhyClEhHjJQQ+9O9mCY8efKN541KZl962YnfUuznRSd3yWHxfaOmCdPQ cQIJVtcyEeYpsqMWv7YzzkvyS9j4VB/1IlqY10KaU5ZESSot39eGcuzbQHD+SQRYfK H2qwbC6juhljA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add device tree node for GPCDMA controller on Tegra186 target and Tegra194 target. Signed-off-by: Rajesh Gumasta --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 ++++++++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 ++++++++++++++++++++++++ 3 files changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 2fcaa2e..56ed8d8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -54,6 +54,10 @@ }; }; + dma@2600000 { + status = "okay"; + }; + memory-controller@2c00000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 58100fb..91bb17e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -70,6 +70,52 @@ snps,rxpbl = <8>; }; + gpcdma: dma@2600000 { + compatible = "nvidia,tegra186-gpcdma"; + reg = <0x0 0x2600000 0x0 0x210000>; + resets = <&bpmp TEGRA186_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + nvidia,start-dma-channel-index = <1>; + dma-channels = <31>; + status = "disabled"; + }; + aconnect { compatible = "nvidia,tegra186-aconnect", "nvidia,tegra210-aconnect"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 4bc187a..0bd67bd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -68,6 +68,50 @@ snps,rxpbl = <8>; }; + gpcdma: dma@2600000 { + compatible = "nvidia,tegra194-gpcdma"; + reg = <0x0 0x2600000 0x0 0x210000>; + resets = <&bpmp TEGRA194_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + nvidia,start-dma-channel-index = <1>; + dma-channels = <31>; + status = "disabled"; + }; + aconnect@2900000 { compatible = "nvidia,tegra194-aconnect", "nvidia,tegra210-aconnect";