[RFC,v10,7/9] MAINTAINERS: Add Tegra Video driver section

Message ID	1587700513-28449-8-git-send-email-skomatineni@nvidia.com
State	Changes Requested
Headers	show Return-Path: <linux-tegra-owner@vger.kernel.org> TLS: TLSv1.2, DES-CBC3-SHA) id <B5ea262ef0001>; Thu, 23 Apr 2020 20:54:23 -0700 From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <skomatineni@nvidia.com>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <frankc@nvidia.com>, <hverkuil@xs4all.nl>, <sakari.ailus@iki.fi>, <helen.koike@collabora.com> CC: <digetx@gmail.com>, <sboyd@kernel.org>, <linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [RFC PATCH v10 7/9] MAINTAINERS: Add Tegra Video driver section Date: Thu, 23 Apr 2020 20:55:11 -0700 Message-ID: <1587700513-28449-8-git-send-email-skomatineni@nvidia.com> In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk
Series	[RFC,v10,1/9] arm64: tegra: Fix sor powergate clocks and reset \| expand [RFC,v10,0/9] Add Tegra driver for video capture [RFC,v10,1/9] arm64: tegra: Fix sor powergate clocks and reset [RFC,v10,2/9] arm64: tegra: Add reset-cells to mc [RFC,v10,3/9] dt-bindings: clock: tegra: Add clk id for CSI TPG clock [RFC,v10,4/9] clk: tegra: Add Tegra210 CSI TPG clock gate [RFC,v10,5/9] dt-binding: tegra: Add VI and CSI bindings [RFC,v10,6/9] media: tegra: Add Tegra210 Video input driver [RFC,v10,7/9] MAINTAINERS: Add Tegra Video driver section [RFC,v10,8/9] dt-bindings: reset: Add ID for Tegra210 VI reset [RFC,v10,9/9] arm64: tegra: Add Tegra VI CSI support in device tree

Message ID

1587700513-28449-8-git-send-email-skomatineni@nvidia.com

State

Changes Requested

Headers

From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <skomatineni@nvidia.com>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>, <frankc@nvidia.com>, <hverkuil@xs4all.nl>,
        <sakari.ailus@iki.fi>, <helen.koike@collabora.com>
CC: <digetx@gmail.com>, <sboyd@kernel.org>,
        <linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
Subject: [RFC PATCH v10 7/9] MAINTAINERS: Add Tegra Video driver section
Date: Thu, 23 Apr 2020 20:55:11 -0700
Message-ID: <1587700513-28449-8-git-send-email-skomatineni@nvidia.com>
In-Reply-To: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com>
References: <1587700513-28449-1-git-send-email-skomatineni@nvidia.com>
MIME-Version: 1.0
Content-Type: text/plain
Sender: linux-tegra-owner@vger.kernel.org
Precedence: bulk

Series

[RFC,v10,1/9] arm64: tegra: Fix sor powergate clocks and reset | expand

Commit Message

Sowjanya Komatineni April 24, 2020, 3:55 a.m. UTC

Add maintainers and mailing list entries to Tegra Video driver section.

Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 MAINTAINERS | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 973b7db..795b201 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16644,6 +16644,16 @@  M:	Laxman Dewangan <ldewangan@nvidia.com>
 S:	Supported
 F:	drivers/spi/spi-tegra*
 
+TEGRA VIDEO DRIVER
+M:	Thierry Reding <thierry.reding@gmail.com>
+M:	Jonathan Hunter <jonathanh@nvidia.com>
+M:	Sowjanya Komatineni <skomatineni@nvidia.com>
+L:	linux-media@vger.kernel.org
+L:	linux-tegra@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+F:	drivers/staging/media/tegra/
+
 TEGRA XUSB PADCTL DRIVER
 M:	JC Kuo <jckuo@nvidia.com>
 S:	Supported

[RFC,v10,7/9] MAINTAINERS: Add Tegra Video driver section

Commit Message

Patch