From patchwork Wed Apr 15 02:57:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1270827 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=SziGpGhJ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4926Vz3XjWz9sQx for ; Wed, 15 Apr 2020 12:58:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729431AbgDOC54 (ORCPT ); Tue, 14 Apr 2020 22:57:56 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:3781 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729115AbgDOC5w (ORCPT ); Tue, 14 Apr 2020 22:57:52 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 14 Apr 2020 19:56:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 14 Apr 2020 19:57:51 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 14 Apr 2020 19:57:51 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 15 Apr 2020 02:57:51 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 15 Apr 2020 02:57:51 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.171.241]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 14 Apr 2020 19:57:51 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v7 9/9] arm64: tegra: Add Tegra VI CSI support in device tree Date: Tue, 14 Apr 2020 19:57:43 -0700 Message-ID: <1586919463-30542-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> References: <1586919463-30542-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1586919413; bh=yB3b29VbNFtTvMcPZCMVxLppaVECoZp9WEY70dWiuUY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=SziGpGhJe980GifGZkqDEWB8sMEsV/YcQhL0tGJ5mSYGCelUxz/IhdB7ZmiVt+vdR 69DcoiLaInltbB98jxe8gLeJxwml0SqzLLPjnMcJVlzzZrsu/35pxuQSqDCucPjPyW FVpAs2RXLycyJBMSW343mL6V7XZIi80gg3o3yKk41QztmmV7y6yLvd0RxorNu97f/t hEVJVcbkrR5FIcCEObYIN8+mmBm2wQ7N5GHmsRul+PkjvbUWp7w0ilRcGj54BiX202 ZkjBR83hGgnb05VgBkrMewCXwnx1xFFN0G6npZxNftn+S+m4lFFo01UulkXiSFFM8E 7Y7COsPM3lDfg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra210 contains VI controller for video input capture from MIPI CSI camera sensors and also supports built-in test pattern generator. CSI ports can be one-to-one mapped to VI channels for capturing from an external sensor or from built-in test pattern generator. This patch adds support for VI and CSI and enables them in Tegra210 device tree. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 10 ++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 46 +++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 313a4c2..b57d837 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -14,6 +14,16 @@ status = "okay"; }; + vi@54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + + csi@838 { + status = "okay"; + }; + }; + sor@54580000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 5b1dfd8..cad42a7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -137,9 +137,44 @@ vi@54080000 { compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x00040000>; + reg = <0x0 0x54080000 0x0 0x700>; interrupts = ; status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>, + <972000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; + power-domains = <&pd_sor>; + }; }; tsec@54100000 { @@ -839,6 +874,15 @@ reset-names = "vic"; #power-domain-cells = <0>; }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + resets = <&mc TEGRA210_MC_RESET_VI>, + <&tegra_car TEGRA210_RST_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + #power-domain-cells = <0>; + }; }; sdmmc1_3v3: sdmmc1-3v3 {