diff mbox series

pwm: tegra: Add support for Tegra194

Message ID 1583407653-30059-1-git-send-email-spatra@nvidia.com
State New
Headers show
Series pwm: tegra: Add support for Tegra194 | expand

Commit Message

Sandipan Patra March 5, 2020, 11:27 a.m. UTC
Tegra194 has multiple PWM controllers with each having only one output.

Also the maxmimum frequency is higher than earlier SoCs.

Add support for Tegra194 and specify the number of PWM outputs and
maximum supported frequency using device tree match data.

Signed-off-by: Sandipan Patra <spatra@nvidia.com>
---
 Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 1 +
 drivers/pwm/pwm-tegra.c                                      | 6 ++++++
 2 files changed, 7 insertions(+)

Comments

Uwe Kleine-König March 6, 2020, 7:28 a.m. UTC | #1
On Thu, Mar 05, 2020 at 04:57:33PM +0530, Sandipan Patra wrote:
> Tegra194 has multiple PWM controllers with each having only one output.
> 
> Also the maxmimum frequency is higher than earlier SoCs.
> 
> Add support for Tegra194 and specify the number of PWM outputs and
> maximum supported frequency using device tree match data.
> 
> Signed-off-by: Sandipan Patra <spatra@nvidia.com>

Looks good to me,

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

Thanks
Uwe
Laxman Dewangan March 6, 2020, 9:03 a.m. UTC | #2
On Thursday 05 March 2020 04:57 PM, Sandipan Patra wrote:
> Tegra194 has multiple PWM controllers with each having only one output.
>
> Also the maxmimum frequency is higher than earlier SoCs.
>
> Add support for Tegra194 and specify the number of PWM outputs and
> maximum supported frequency using device tree match data.
>
> Signed-off-by: Sandipan Patra <spatra@nvidia.com>
> ---
>   Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 1 +
>   drivers/pwm/pwm-tegra.c                                      | 6 ++++++
>   2 files changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> index 0a69ead..74c41e3 100644
> --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> @@ -9,6 +9,7 @@ Required properties:
>     - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
>     - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
>     - "nvidia,tegra186-pwm": for Tegra186
> +  - "nvidia,tegra194-pwm": for Tegra194
>   - reg: physical base address and length of the controller's registers
>   - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
>     the cells format.
>

Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Rob Herring March 10, 2020, 9:43 p.m. UTC | #3
On Thu, 5 Mar 2020 16:57:33 +0530, Sandipan Patra wrote:
> Tegra194 has multiple PWM controllers with each having only one output.
> 
> Also the maxmimum frequency is higher than earlier SoCs.
> 
> Add support for Tegra194 and specify the number of PWM outputs and
> maximum supported frequency using device tree match data.
> 
> Signed-off-by: Sandipan Patra <spatra@nvidia.com>
> ---
>  Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 1 +
>  drivers/pwm/pwm-tegra.c                                      | 6 ++++++
>  2 files changed, 7 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>
Jon Hunter March 23, 2020, 11:36 a.m. UTC | #4
On 05/03/2020 11:27, Sandipan Patra wrote:
> Tegra194 has multiple PWM controllers with each having only one output.
> 
> Also the maxmimum frequency is higher than earlier SoCs.
> 
> Add support for Tegra194 and specify the number of PWM outputs and
> maximum supported frequency using device tree match data.
> 
> Signed-off-by: Sandipan Patra <spatra@nvidia.com>
> ---
>  Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 1 +
>  drivers/pwm/pwm-tegra.c                                      | 6 ++++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> index 0a69ead..74c41e3 100644
> --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> @@ -9,6 +9,7 @@ Required properties:
>    - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
>    - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
>    - "nvidia,tegra186-pwm": for Tegra186
> +  - "nvidia,tegra194-pwm": for Tegra194
>  - reg: physical base address and length of the controller's registers
>  - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
>    the cells format.
> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> index aa12fb3..d26ed8f 100644
> --- a/drivers/pwm/pwm-tegra.c
> +++ b/drivers/pwm/pwm-tegra.c
> @@ -282,9 +282,15 @@ static const struct tegra_pwm_soc tegra186_pwm_soc = {
>  	.max_frequency = 102000000UL,
>  };
>  
> +static const struct tegra_pwm_soc tegra194_pwm_soc = {
> +	.num_channels = 1,
> +	.max_frequency = 408000000UL,
> +};
> +
>  static const struct of_device_id tegra_pwm_of_match[] = {
>  	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
>  	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
> +	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
> 


Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index 0a69ead..74c41e3 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -9,6 +9,7 @@  Required properties:
   - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
   - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
   - "nvidia,tegra186-pwm": for Tegra186
+  - "nvidia,tegra194-pwm": for Tegra194
 - reg: physical base address and length of the controller's registers
 - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
   the cells format.
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index aa12fb3..d26ed8f 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -282,9 +282,15 @@  static const struct tegra_pwm_soc tegra186_pwm_soc = {
 	.max_frequency = 102000000UL,
 };
 
+static const struct tegra_pwm_soc tegra194_pwm_soc = {
+	.num_channels = 1,
+	.max_frequency = 408000000UL,
+};
+
 static const struct of_device_id tegra_pwm_of_match[] = {
 	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
 	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
+	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);