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Mon, 28 Oct 2019 12:42:56 +0000 (GMT) From: Anvesh Salveru To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Cc: pankaj.dubey@samsung.com, thierry.reding@gmail.com, jonathanh@nvidia.com, Anvesh Salveru , Rob Herring , Mark Rutland Subject: [PATCH 2/2] arm64: tegra: Add support for ZRX-DC phy property Date: Mon, 28 Oct 2019 18:12:20 +0530 Message-Id: <1572266540-17626-3-git-send-email-anvesh.s@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572266540-17626-1-git-send-email-anvesh.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFIsWRmVeSWpSXmKPExsWy7bCmhm7wo22xBl1XOCzO7lrIajH/yDlW i5ZZi1gsLu+aw2Zxdt5xNovOL7PYLJZev8hksWjrF3aL1r1H2C1+7prH4sDlsWbeGkaPnbPu sntsWtXJ5tHb/I7No2/LKkaPz5vkAtiiuGxSUnMyy1KL9O0SuDIO/drBWDBXsuLP/BeMDYw7 RboYOTkkBEwkvs58xNjFyMUhJLCbUaL7SRMzhPOJUeLa6x/sEM43RolnvxcwwbQ0LDvLBpHY yygx/eBvqKoWJokl1/8yglSxCWhL/Dy6lx3EFhEok5jVdAVsCbPAPkaJKTPOgSWEBdwkjve8 ZQWxWQRUJT70bWcDsXkFXCR2bb/LArFOTuLmuU5mEJtTwFWie+sjFpBBEgI72CT+959lhChy kVj88jUrhC0s8er4FnYIW0riZX8blJ0v0Xt3KZRdIzHlbgdUr73EgStzgIZyAF2nKbF+lz5I mFmAT6L39xMmkLCEAK9ER5sQhKkk0TazGqJRQmLx/JvMELaHROufTdBwmMEo0fXmKvMERtlZ CEMXMDKuYpRMLSjOTU8tNi0wykst1ytOzC0uzUvXS87P3cQIThFaXjsYl53zOcQowMGoxMM7 4fK2WCHWxLLiytxDjBIczEoivBfPAIV4UxIrq1KL8uOLSnNSiw8xSnOwKInzTmK9GiMkkJ5Y kpqdmlqQWgSTZeLglGpgVHx68OrGR5EiynccGJSDyl8Y/i64lKU90c3qn4xYusO3+3ccBWa/ Cl53oqY16PK8X1kXz4vmPGqJrfWYy3c9Vu7uwYW5wYHLsj+y+ljOKv259vae4AAGm23Sv/Mu 7Axx33et+vHVF5N2nty6YPFLfi/fLatMF2S2+Wds6ZAKycx7kxZu8dhHXImlOCPRUIu5qDgR AD7CnfYNAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJLMWRmVeSWpSXmKPExsWy7bCSvG7Qo22xBnf/iluc3bWQ1WL+kXOs Fi2zFrFYXN41h83i7LzjbBadX2axWSy9fpHJYtHWL+wWrXuPsFv83DWPxYHLY828NYweO2fd ZffYtKqTzaO3+R2bR9+WVYwenzfJBbBFcdmkpOZklqUW6dslcGUc+rWDsWCuZMWf+S8YGxh3 inQxcnJICJhINCw7y9bFyMUhJLCbUWLLrzMsEAkJiS97v7JB2MISK/89Z4coamKSWPN6HStI gk1AW+Ln0b3sILaIQJXEgY4+FpAiZoEjjBI/br0A6xYWcJM43vMWrIFFQFXiQ992sDivgIvE ru13obbJSdw818kMYnMKuEp0b30EFhcCqmn6+4p5AiPfAkaGVYySqQXFuem5xYYFhnmp5XrF ibnFpXnpesn5uZsYwQGqpbmD8fKS+EOMAhyMSjy8L65uixViTSwrrsw9xCjBwawkwnvxDFCI NyWxsiq1KD++qDQntfgQozQHi5I479O8Y5FCAumJJanZqakFqUUwWSYOTqkGxvaU/g3Rf6Xt Gy7tStB7ezp3zuQ7YVKvrpc/XLD0ZefXuIPuqcJr/HU0mE//6H787/V+J41DPZ8OlT8s8/58 SHyb0g6niZ7veO3/S8lObS/4fflMwrfL5ZYbNzQZSMuKCdyeecGn29p1l39/yFPVN76XWdyl +sq8FQ9xlbyZosG93udKziMWKyWW4oxEQy3mouJEANVhKEpMAgAA X-CMS-MailID: 20191028124258epcas5p17861f4fdb40385a184fc397f45c898a5 X-Msg-Generator: CA CMS-TYPE: 105P X-CMS-RootMailID: 20191028124258epcas5p17861f4fdb40385a184fc397f45c898a5 References: <1572266540-17626-1-git-send-email-anvesh.s@samsung.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org DesignWare controller driver provides the support to handle the PHYs which are compliant to ZRX-DC specification based on "snps,phy-zrxdc-compliant" DT property. So, add "snps,phy-zrxdc-compliant" property in tegra pcie controller DT nodes. CC: Rob Herring CC: Mark Rutland Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey --- Depends on the following patch: https://patchwork.kernel.org/patch/11215241/ https://patchwork.kernel.org/patch/11215239/ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 3c0cf54f0aab..bf2dbf84c8c9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1194,6 +1194,7 @@ ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + snps,phy-zrxdc-compliant; }; pcie@14120000 { @@ -1240,6 +1241,7 @@ ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + snps,phy-zrxdc-compliant; }; pcie@14140000 { @@ -1286,6 +1288,7 @@ ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ + snps,phy-zrxdc-compliant; }; pcie@14160000 { @@ -1332,6 +1335,7 @@ ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + snps,phy-zrxdc-compliant; }; pcie@14180000 { @@ -1378,6 +1382,7 @@ ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + snps,phy-zrxdc-compliant; }; pcie@141a0000 { @@ -1428,6 +1433,7 @@ ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ + snps,phy-zrxdc-compliant; }; sysram@40000000 {