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[1/2] PCI: tegra: Remove support for ZRX-DC compliant PHY from platform driver

Message ID 1572266540-17626-2-git-send-email-anvesh.s@samsung.com
State New
Headers show
Series Add support for ZRX-DC phy property | expand

Commit Message

Anvesh Salveru Oct. 28, 2019, 12:42 p.m. UTC
As part of dw_pcie_setup(), PHYs which are compliant to ZRX-DC
specification are already handled based on "snps,phy-zrxdc-compliant"
property in controller DT node. So, instead of handling ZRX-DC
compliant settings in each platform driver, remove this driver
specific code.

CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
CC: Andrew Murray <andrew.murray@arm.com>
CC: Bjorn Helgaas <bhelgaas@google.com>
CC: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Anvesh Salveru <anvesh.s@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Depends on the following patch:

 drivers/pci/controller/dwc/pcie-tegra194.c | 4 ----
 1 file changed, 4 deletions(-)
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diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index f89f5acee72d..f3a6ea89b8a8 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -782,10 +782,6 @@  static void tegra_pcie_prepare_host(struct pcie_port *pp)
-	val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
-	dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
 	if (pcie->update_fc_fixup) {
 		val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
 		val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;