From patchwork Wed Sep 4 04:42:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1157449 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="jhQLbAuB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46NWRY2rP1z9sP7 for ; Wed, 4 Sep 2019 14:43:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728604AbfIDEnc (ORCPT ); Wed, 4 Sep 2019 00:43:32 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:7319 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728595AbfIDEnc (ORCPT ); Wed, 4 Sep 2019 00:43:32 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 03 Sep 2019 21:43:34 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 03 Sep 2019 21:43:31 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 03 Sep 2019 21:43:31 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 4 Sep 2019 04:43:31 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 4 Sep 2019 04:43:31 +0000 Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 03 Sep 2019 21:43:30 -0700 From: Krishna Yarlagadda To: , , , , , , CC: , , , , Krishna Yarlagadda , Shardar Shariff Md Subject: [PATCH V2 04/12] serial: tegra: report error to upper tty layer Date: Wed, 4 Sep 2019 10:12:59 +0530 Message-ID: <1567572187-29820-5-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567572187-29820-1-git-send-email-kyarlagadda@nvidia.com> References: <1567572187-29820-1-git-send-email-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1567572214; bh=HAO/3tHNmsgBI1WiOn5FkmB03zXOUH5H8G2INtCZe6g=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=jhQLbAuBYin85On3xPsqt1bAcQkj/cCX2NKEqRufFhT/4LmvwmQ09zU0nBDRKmhNN KaPXOKTuOCg7Ggt1WmM2itoFKy0ARInsQqtrz4jWuqDrjoxd1BKlcS+e2Saza6vogX vY58MTGgF0y0zhgWU7s4qOaDwXmwiCXqxvMCDjmX/9jTKTD6ZP5wyFtiUdqEZinyhY yTaiSx3yHQfrYJyjWZsCkrHpAdsHXnTJcgnGwifGSgGf+8+0gAw2U0dIYdrxw4wyQL FdYLTaGGWQIXzzPJj1u8n4Os4Ht66fVCJ7Z8l9pVMlDufKMg00fNCqDxfHGqXfudm8 NRyS1/54oPyuQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Report overrun/parity/frame/break errors to top tty layer. Add support to ignore break character if IGNBRK is set. Signed-off-by: Shardar Shariff Md Signed-off-by: Krishna Yarlagadda --- drivers/tty/serial/serial-tegra.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c index 4cd6d5f..c3f9913 100644 --- a/drivers/tty/serial/serial-tegra.c +++ b/drivers/tty/serial/serial-tegra.c @@ -373,13 +373,21 @@ static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup, tup->uport.icount.frame++; dev_err(tup->uport.dev, "Got frame errors\n"); } else if (lsr & UART_LSR_BI) { - dev_err(tup->uport.dev, "Got Break\n"); - tup->uport.icount.brk++; - /* If FIFO read error without any data, reset Rx FIFO */ + /* + * Break error + * If FIFO read error without any data, reset Rx FIFO + */ if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE)) tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR); + if (tup->uport.ignore_status_mask & UART_LSR_BI) + return TTY_BREAK; + flag = TTY_BREAK; + tup->uport.icount.brk++; + dev_dbg(tup->uport.dev, "Got Break\n"); } + uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag); } + return flag; } @@ -561,6 +569,9 @@ static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup, break; flag = tegra_uart_decode_rx_error(tup, lsr); + if (flag != TTY_NORMAL) + continue; + ch = (unsigned char) tegra_uart_read(tup, UART_RX); tup->uport.icount.rx++; @@ -1223,6 +1234,8 @@ static void tegra_uart_set_termios(struct uart_port *u, /* Ignore all characters if CREAD is not set */ if ((termios->c_cflag & CREAD) == 0) tup->uport.ignore_status_mask |= UART_LSR_DR; + if (termios->c_iflag & IGNBRK) + tup->uport.ignore_status_mask |= UART_LSR_BI; spin_unlock_irqrestore(&u->lock, flags); }