diff mbox series

[07/14] serial: tegra: add compatible for new chips

Message ID 1565609303-27000-8-git-send-email-kyarlagadda@nvidia.com
State New
Headers show
Series serial: tegra: Tegra186 support and fixes | expand

Commit Message

Krishna Yarlagadda Aug. 12, 2019, 11:28 a.m. UTC
Add new compatible string for Tegra186. It differs from earlier chips
as it has fifo mode enable check and 8 byte dma buffer.
Add new compatible string for Tegra194. Tegra194 has different error
tolerance levels for baud rate compared to older chips.

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
---
 Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Thierry Reding Aug. 13, 2019, 9:55 a.m. UTC | #1
On Mon, Aug 12, 2019 at 04:58:16PM +0530, Krishna Yarlagadda wrote:
> Add new compatible string for Tegra186. It differs from earlier chips
> as it has fifo mode enable check and 8 byte dma buffer.
> Add new compatible string for Tegra194. Tegra194 has different error
> tolerance levels for baud rate compared to older chips.
> 
> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> ---
>  Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

I think device tree binding patches are supposed to start with
"dt-binding: ...".

Also: "fifo" -> "FIFO" and "dma" -> "DMA" in the commit message.

> 
> diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> index d7edf73..187ec78 100644
> --- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> @@ -1,7 +1,8 @@
>  NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
>  
>  Required properties:
> -- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
> +- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart",
> +  nvidia,tegra186-hsuart, nvidia,tegra194-hsuart.

Please use quotes around the compatible strings like the existing ones.
Also, I think it might be better to list these explicitly rather than
just give a list of potential values. As it is right now, it's
impossible to tell whether this is meant to say "should be all of these"
or whether it is meant to say "should be one of these".

Thierry

>  - reg: Should contain UART controller registers location and length.
>  - interrupts: Should contain UART controller interrupts.
>  - clocks: Must contain one entry, for the module clock.
> -- 
> 2.7.4
>
Krishna Yarlagadda Aug. 27, 2019, 9:29 a.m. UTC | #2
> -----Original Message-----
> From: Thierry Reding <thierry.reding@gmail.com>
> Sent: Tuesday, August 13, 2019 3:26 PM
> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> Cc: gregkh@linuxfoundation.org; robh+dt@kernel.org;
> mark.rutland@arm.com; Jonathan Hunter <jonathanh@nvidia.com>; Laxman
> Dewangan <ldewangan@nvidia.com>; jslaby@suse.com; linux-
> serial@vger.kernel.org; devicetree@vger.kernel.org; linux-
> tegra@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 07/14] serial: tegra: add compatible for new chips
> 
> On Mon, Aug 12, 2019 at 04:58:16PM +0530, Krishna Yarlagadda wrote:
> > Add new compatible string for Tegra186. It differs from earlier chips
> > as it has fifo mode enable check and 8 byte dma buffer.
> > Add new compatible string for Tegra194. Tegra194 has different error
> > tolerance levels for baud rate compared to older chips.
> >
> > Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> > ---
> >  Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt |
> > 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> I think device tree binding patches are supposed to start with
> "dt-binding: ...".
> 
> Also: "fifo" -> "FIFO" and "dma" -> "DMA" in the commit message.
> 
> >
> > diff --git
> > a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> > b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> > index d7edf73..187ec78 100644
> > ---
> > a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
> > +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.t
> > +++ xt
> > @@ -1,7 +1,8 @@
> >  NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
> >
> >  Required properties:
> > -- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
> > +- compatible : should be "nvidia,tegra30-hsuart",
> > +"nvidia,tegra20-hsuart",
> > +  nvidia,tegra186-hsuart, nvidia,tegra194-hsuart.
> 
> Please use quotes around the compatible strings like the existing ones.
> Also, I think it might be better to list these explicitly rather than just give a list
> of potential values. As it is right now, it's impossible to tell whether this is
> meant to say "should be all of these"
> or whether it is meant to say "should be one of these".
> 
> Thierry
> 
Will update in next version.
KY
> >  - reg: Should contain UART controller registers location and length.
> >  - interrupts: Should contain UART controller interrupts.
> >  - clocks: Must contain one entry, for the module clock.
> > --
> > 2.7.4
> >
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index d7edf73..187ec78 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -1,7 +1,8 @@ 
 NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
 
 Required properties:
-- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
+- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart",
+  nvidia,tegra186-hsuart, nvidia,tegra194-hsuart.
 - reg: Should contain UART controller registers location and length.
 - interrupts: Should contain UART controller interrupts.
 - clocks: Must contain one entry, for the module clock.