From patchwork Mon Aug 12 11:28:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1145660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="AAPN71YV"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 466YWp63GPz9sPL for ; Mon, 12 Aug 2019 21:28:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728415AbfHLL2x (ORCPT ); Mon, 12 Aug 2019 07:28:53 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:4775 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727936AbfHLL2w (ORCPT ); Mon, 12 Aug 2019 07:28:52 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 12 Aug 2019 04:28:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 12 Aug 2019 04:28:51 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 12 Aug 2019 04:28:51 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 12 Aug 2019 11:28:51 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 12 Aug 2019 11:28:51 +0000 Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 12 Aug 2019 04:28:50 -0700 From: Krishna Yarlagadda To: , , , , , , CC: , , , , Ahung Cheng , Krishna Yarlagadda Subject: [PATCH 04/14] serial: tegra: protect IER against LCR.DLAB Date: Mon, 12 Aug 2019 16:58:13 +0530 Message-ID: <1565609303-27000-5-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565609303-27000-1-git-send-email-kyarlagadda@nvidia.com> References: <1565609303-27000-1-git-send-email-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1565609333; bh=ADUXU22pbKxAc6su3ZyKW+PXLicjlm3CyfngVyySigY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=AAPN71YVilUkhMM4ZQLASP2z7l32sRtguhSU2VWXBOK7/hLj2llV8hCl7PZ+IR3ov l/23CpAoXY791yeV1Uv089//c9X94MFaQhXymycIa1jry2/N3YyXjdVQk4qVIUaByn 1GKqZBzti8q/PPEh9LdqG4h0e4oP1KvNN5nHHDSjajcN7XcBF/ZU3NoXLNRPn5WCuV IMLSU8/lC0xZv0GMthmETTJUs7K+sFnYovKV/7sl9BISOyPhOlSDz4mmDyw6GjSVny owwBuGfWElnB06LjTO/mf/oGInzwto8K4ry8M1NdNvujSviOsPyPB9hMtsWKmHGz8l 0fuNceNWr0pWg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Ahung Cheng The IER and DLH registers occupy the same address space, selected by the LCR.DLAB bit. Hence, add port lock to protect IER when LCR.DLAB bit is set. Signed-off-by: Ahung Cheng Signed-off-by: Krishna Yarlagadda Acked-by: Thierry Reding --- drivers/tty/serial/serial-tegra.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c index d908465..ae7225c 100644 --- a/drivers/tty/serial/serial-tegra.c +++ b/drivers/tty/serial/serial-tegra.c @@ -296,6 +296,7 @@ static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) unsigned long rate; unsigned int divisor; unsigned long lcr; + unsigned long flags; int ret; if (tup->current_baud == baud) @@ -315,6 +316,7 @@ static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) divisor = DIV_ROUND_CLOSEST(rate, baud * 16); } + spin_lock_irqsave(&tup->uport.lock, flags); lcr = tup->lcr_shadow; lcr |= UART_LCR_DLAB; tegra_uart_write(tup, lcr, UART_LCR); @@ -327,6 +329,7 @@ static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud) /* Dummy read to ensure the write is posted */ tegra_uart_read(tup, UART_SCR); + spin_unlock_irqrestore(&tup->uport.lock, flags); tup->current_baud = baud;