From patchwork Fri Mar 22 12:13:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 1061120 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="kJ/dDzQo"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44QjlX0wVtz9s7h for ; Fri, 22 Mar 2019 23:34:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731035AbfCVMNZ (ORCPT ); Fri, 22 Mar 2019 08:13:25 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:1493 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389445AbfCVMNY (ORCPT ); Fri, 22 Mar 2019 08:13:24 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 22 Mar 2019 05:13:22 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 22 Mar 2019 05:13:24 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 22 Mar 2019 05:13:24 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 22 Mar 2019 12:13:23 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 22 Mar 2019 12:13:23 +0000 Received: from linux.nvidia.com (Not Verified[10.24.34.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 22 Mar 2019 05:13:23 -0700 From: Sameer Pujar To: , , , , CC: , , , Sameer Pujar Subject: [PATCH v5 3/3] irqchip/gic-pm: fix suspend handling Date: Fri, 22 Mar 2019 17:43:05 +0530 Message-ID: <1553256785-20333-4-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553256785-20333-1-git-send-email-spujar@nvidia.com> References: <1553256785-20333-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553256802; bh=k87J48y63sq2y29X2S5UwTLdLFVjaJc4AB0sNyd3f7c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=kJ/dDzQokJ4LOCIcfNcFJUYIsW4oMB6VGotqfTikWgGT7iHj8yi/5SSEgOMMLmiGS PdJfv7x0S7AuZptf7VqTpx9XNPxbhHNzUW0BfqiY5lGPGyrZYAMV02iw4fb29QVhLj N6EN8ygwmYYjhvpMm3GbDbgGK6rFpsHhRFotVZSK31pLvlMh3ZH1WSF21yz/hEw4S1 RaffTG16ACd/PSUXpmTAEN5cr+nSE48DfHFcITR8SqLpXgsZYZyFCpB+/m8OFmwB/3 ILRJhaQIhISumiJ5grR1TNQWJ3dAK8xo6zF93+tvUTg0O0sKRngxURJ547ZjkH91sp aG/yWVrU5s/FA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org If interrupts are enabled for a non-root GIC device that uses the gic-pm driver, when system suspend occurs, the current interrupt state is not saved and restored correctly and so interrupts do not work again on resuming the system. Add a late suspend handler to save and restore the state for these devices. Suggested-by: Jonathan Hunter Signed-off-by: Sameer Pujar Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- drivers/irqchip/irq-gic-pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/irq-gic-pm.c b/drivers/irqchip/irq-gic-pm.c index 069cf4c..c4aac09 100644 --- a/drivers/irqchip/irq-gic-pm.c +++ b/drivers/irqchip/irq-gic-pm.c @@ -142,6 +142,8 @@ static int gic_probe(struct platform_device *pdev) static const struct dev_pm_ops gic_pm_ops = { SET_RUNTIME_PM_OPS(gic_runtime_suspend, gic_runtime_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) }; static const char * const gic400_clocks[] = {