From patchwork Fri Mar 22 12:13:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 1061121 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Jeru1D5S"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44Qjlk4vXtz9sNq for ; Fri, 22 Mar 2019 23:34:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731438AbfCVMeg (ORCPT ); Fri, 22 Mar 2019 08:34:36 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:11005 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389729AbfCVMNR (ORCPT ); Fri, 22 Mar 2019 08:13:17 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 22 Mar 2019 05:13:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 22 Mar 2019 05:13:17 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 22 Mar 2019 05:13:17 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 22 Mar 2019 12:13:16 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 22 Mar 2019 12:13:16 +0000 Received: from linux.nvidia.com (Not Verified[10.24.34.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 22 Mar 2019 05:13:16 -0700 From: Sameer Pujar To: , , , , CC: , , , Sameer Pujar Subject: [PATCH v5 1/3] arm64: tegra: select ARM_GIC_PM Date: Fri, 22 Mar 2019 17:43:03 +0530 Message-ID: <1553256785-20333-2-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553256785-20333-1-git-send-email-spujar@nvidia.com> References: <1553256785-20333-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553256795; bh=k1VYKlL7Pc3Cegz0kU3hxrGvJ/auvTTD3wbsfyVSEbo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=Jeru1D5S+t7cF2ODfGZawzhh2fphex9Mr7znRLSKMxaqphjZwm21uMxT0bvRuC3QG HJa4/6ZqmadFquXHPwAk/O/8mIBoVsDQpN1561BjPgWXhE4IpJN1oKQPXI1vkslZk3 G3sd8J4AUdQ38yjLjYbSs9Wdl+JaxsCLD5B4hAuOVC0I2zxW7sSqL/BSCYG8DIg6hi N9rqT0Ix+BLK1LTn+K12d/OqbJ7p+Guv5EyDiEXJxJBXEFsNwUeqlr3bWmSDYyBlLZ 1PMw4ehLmBq+9xhomgpHqkU/ZjWcYbJPo3cDrdiBvmAaMbfVSjkFA5P2c9cJ/DaUmu MnLGdAZaFumxg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable ARM_GIC_PM for 64-bit Tegra devices. This is required to ensure that the driver gets built into kernel and helps to register the AGIC device when enabled in DT. Signed-off-by: Sameer Pujar Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 70498a0..64c73c2 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -218,6 +218,7 @@ config ARCH_TEGRA select PM select PM_GENERIC_DOMAINS select RESET_CONTROLLER + select ARM_GIC_PM help This enables support for the NVIDIA Tegra SoC family.