Message ID | 1552513552-23423-8-git-send-email-skomatineni@nvidia.com |
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State | Changes Requested |
Headers | show
Return-Path: <linux-tegra-owner@vger.kernel.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Drt1eLJi"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44KQQS6XxWz9sD4 for <incoming@patchwork.ozlabs.org>; Thu, 14 Mar 2019 08:46:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726496AbfCMVqX (ORCPT <rfc822;incoming@patchwork.ozlabs.org>); Wed, 13 Mar 2019 17:46:23 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1301 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727572AbfCMVqB (ORCPT <rfc822;linux-tegra@vger.kernel.org>); Wed, 13 Mar 2019 17:46:01 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id <B5c897a1a0001>; Wed, 13 Mar 2019 14:46:02 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 13 Mar 2019 14:46:00 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 13 Mar 2019 14:46:00 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 13 Mar 2019 21:46:00 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 13 Mar 2019 21:46:00 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.103.74]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id <B5c897a180000>; Wed, 13 Mar 2019 14:46:00 -0700 From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <adrian.hunter@intel.com>, <ulf.hansson@linaro.org>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <riteshh@codeaurora.org> CC: <skomatineni@nvidia.com>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <anrao@nvidia.com>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH V3 08/10] mmc: cqhci: add CQHCI_SSC1 register CBC field mask Date: Wed, 13 Mar 2019 14:45:50 -0700 Message-ID: <1552513552-23423-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552513552-23423-1-git-send-email-skomatineni@nvidia.com> References: <1552513552-23423-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1552513562; bh=xxbHJ05YNemsYzdi0Ka810OXVUmw1xCjFx/00R2aCSM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Drt1eLJihg7VWHzdHL0WlgFZUYhWDHbrLQhcgM9Uq7qq+SEz/LbQsazXSqS/7nvIB d84bn0p8p2r323xIERvhuK0wLBGMuj8vWm2hysiXki9uWoMLmhz/I4jvBXfKD9cHyR FPAOAVPzcnFCRHgicNeHca/gKgOyJlVmg9s3l3BtQRIEJX7gpybebhYnuLt5ta4NMb VtpyGXrGocU+kcnMOdhVia+J5QMzLXRikZ8aaGohNhksjf+SyBeRZuwPOPLPWFnXrE nwFJ4aEBJrlJxOWW/eG7X/ETkV/owb/gy7CYzHiOd9emywO7HJjtG7i9t3C7Aal4Hb VkdugkQhEVV9Q== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: <linux-tegra.vger.kernel.org> X-Mailing-List: linux-tegra@vger.kernel.org |
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[V3,01/10] mmc: tegra: fix ddr signaling for non-ddr modes
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diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h index 8c8ec6f01c45..6f2b35e5f47e 100644 --- a/drivers/mmc/host/cqhci.h +++ b/drivers/mmc/host/cqhci.h @@ -88,6 +88,7 @@ /* send status config 1 */ #define CQHCI_SSC1 0x40 +#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16) /* send status config 2 */ #define CQHCI_SSC2 0x44