From patchwork Tue Feb 5 11:16:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 1036645 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="gGe3KpN6"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43v28y5XQGz9sMp for ; Tue, 5 Feb 2019 22:17:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726065AbfBELRG (ORCPT ); Tue, 5 Feb 2019 06:17:06 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:8718 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726031AbfBELRG (ORCPT ); Tue, 5 Feb 2019 06:17:06 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 05 Feb 2019 03:16:34 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 05 Feb 2019 03:17:04 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 05 Feb 2019 03:17:04 -0800 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 5 Feb 2019 11:17:04 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 5 Feb 2019 11:17:04 +0000 Received: from linux.nvidia.com (Not Verified[10.24.34.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 05 Feb 2019 03:17:03 -0800 From: Sameer Pujar To: , CC: , , , , , Sameer Pujar Subject: [PATCH] ARM: tegra: enforce PM requirement Date: Tue, 5 Feb 2019 16:46:58 +0530 Message-ID: <1549365418-26283-1-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1549365394; bh=upWYMJJj7VUHNj03N/Pj0XxtmbTt4ge25Lw5rdzXDSU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:Content-Type; b=gGe3KpN6AZbmVjPTksdRhpW3lBHlVaT1o9Zsw5IHx/XU7KKgV9lhpJYVjEhCM9nPI UDgHuE17tF8Gt+ZlsD5jFgErLC+v9U0M++WhJVGeADLxondhW8kZBBumKbzPTEL2lc pos2vTtcIqmX0kLSTeZfeGAv6J9VlAoIWqbc+JTsWbHcVsUYyTa6UKsp6Suq7p1NcK OfFQdVhs8dVvWVmXHxb8DFnmCJ1bvoziQsgfLm7S86PsHD/LGdyi/xjSYjIDI1+n9X GHmXrwb9UxJ7PCyo9cmtZcd9mEMCUIV2QnqEq3kNavKJnBE+1k2l8CpvFWTHZG+eO7 +zTB6aPKU8BMw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Drivers need to handle !PM case with work arounds for managing clocks and power explicitly, which is not really necessary when PM support on tegra is in good shape. In fact ARM 64-bit tegra platforms enforce PM support and there is no reason why this cannot be done for 32-bit. This patch selects PM unconditionally and drivers can rely on runtime PM framework for clock and power management. Signed-off-by: Sameer Pujar Reviewed-by: Thierry Reding Reviewed-by: Jonathan Hunter --- arch/arm/mach-tegra/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 7f3b83e..51a8fa3 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -10,6 +10,7 @@ menuconfig ARCH_TEGRA select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select PINCTRL + select PM select PM_OPP select ARCH_HAS_RESET_CONTROLLER select RESET_CONTROLLER