From patchwork Wed Jan 16 20:50:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: navneet kumar X-Patchwork-Id: 1026202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="paqdmjcR"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43fzqk0750z9sDX for ; Thu, 17 Jan 2019 07:50:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727279AbfAPUuY (ORCPT ); Wed, 16 Jan 2019 15:50:24 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:18689 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726123AbfAPUuY (ORCPT ); Wed, 16 Jan 2019 15:50:24 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 16 Jan 2019 12:49:53 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 16 Jan 2019 12:50:23 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 16 Jan 2019 12:50:23 -0800 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 16 Jan 2019 20:50:23 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 16 Jan 2019 20:50:22 +0000 Received: from navneetk-dev-ubuntu16.nvidia.com (Not Verified[172.17.173.90]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 16 Jan 2019 12:50:22 -0800 From: Navneet Kumar To: , CC: , , , Subject: [PATCH 1/5] iommu/tegra-smmu: Fix domain_alloc Date: Wed, 16 Jan 2019 12:50:10 -0800 Message-ID: <1547671814-30088-1-git-send-email-navneetk@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1547671793; bh=FE3CqLqEezD/aJNvSPJ+Auu2NM5nSHDi+Oxis4w/7Wo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=paqdmjcRL55OR5v/frizOHetQXiVMpGVbnLBZzAa6zri85uNPGYfE96GfluQRi4e5 /A+vCHGxelcE968w25QM6NJqvtJeLZNuty4Q72olb/woxPD2cbfWY33w35JpYIsjBS mDgzrIKmYhhDGTC4Y7Ou+RXoCG6TUVVI6NltOd7JHcIyhK7REvajrLJODwzd0ofCAE Fh/sdjjEGwFD3cRTH+F5+p3NgaO30cUfGmbINWAF+KBFv7vEo+8ipxJg0f26s/2745 xdCDZDHPrRW35uW44eLIn510P7Cqxf1rQn/DXRBErw4bibLXUyKMGYe5n2pQWf3tWq fJBtMik27YQVg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org * Allocate dma iova cookie for a domain while adding dma iommu devices. * Perform a stricter check for domain type parameter. Signed-off-by: Navneet Kumar --- drivers/iommu/tegra-smmu.c | 43 +++++++++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 543f7c9..ee4d8a8 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -271,8 +272,10 @@ static bool tegra_smmu_capable(enum iommu_cap cap) static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) { struct tegra_smmu_as *as; + int ret; - if (type != IOMMU_DOMAIN_UNMANAGED) + if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA && + type != IOMMU_DOMAIN_IDENTITY) return NULL; as = kzalloc(sizeof(*as), GFP_KERNEL); @@ -281,26 +284,22 @@ static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; + ret = (type == IOMMU_DOMAIN_DMA) ? iommu_get_dma_cookie(&as->domain) : + -ENODEV; + if (ret) + goto free_as; + as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO); - if (!as->pd) { - kfree(as); - return NULL; - } + if (!as->pd) + goto put_dma_cookie; as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL); - if (!as->count) { - __free_page(as->pd); - kfree(as); - return NULL; - } + if (!as->count) + goto free_pd_range; as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL); - if (!as->pts) { - kfree(as->count); - __free_page(as->pd); - kfree(as); - return NULL; - } + if (!as->pts) + goto free_pts; /* setup aperture */ as->domain.geometry.aperture_start = 0; @@ -308,6 +307,18 @@ static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) as->domain.geometry.force_aperture = true; return &as->domain; + +free_pts: + kfree(as->pts); +free_pd_range: + __free_page(as->pd); +put_dma_cookie: + if (type == IOMMU_DOMAIN_DMA) + iommu_put_dma_cookie(&as->domain); +free_as: + kfree(as); + + return NULL; } static void tegra_smmu_domain_free(struct iommu_domain *domain)