From patchwork Thu Jan 3 10:04:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 1020225 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="IyAJX22k"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43Vk8K4BKsz9s9G for ; Thu, 3 Jan 2019 21:06:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730695AbfACKGI (ORCPT ); Thu, 3 Jan 2019 05:06:08 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19851 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730589AbfACKGH (ORCPT ); Thu, 3 Jan 2019 05:06:07 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 03 Jan 2019 02:05:46 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 03 Jan 2019 02:06:06 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 03 Jan 2019 02:06:06 -0800 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 3 Jan 2019 10:06:06 +0000 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 3 Jan 2019 10:06:06 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 3 Jan 2019 10:06:06 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.65.96]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 03 Jan 2019 02:06:05 -0800 From: Nagarjuna Kristam To: , , , CC: , , "Nagarjuna Kristam" Subject: [PATCH 4/8] arm64: tegra: Add xudc node for Tegra210 Date: Thu, 3 Jan 2019 15:34:55 +0530 Message-ID: <1546509899-5071-5-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1546509899-5071-1-git-send-email-nkristam@nvidia.com> References: <1546509899-5071-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1546509947; bh=meUHcfWCL3JBn9faEPcw5sjdGizP1RropmigLTFF/AU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=IyAJX22kDVRAL54Fum/0bUiouOD3iJHED+D2Q6UXCPPerWIas2Ajbuy4bmVcEPDmm GmzjhXCEh3Fs+70gPwz7fEUSotimqpuceElk14Wnr/A1TuloZY5R4eHW4QNntTbk68 y0ExUr9FdXzp2yw0o8yuVOmfJ0IDULwxTGa7EP1ou+kvcEcqBHfvMTaGDCe7wo5+VG 4ULx2tmw1mGFCzPA7w2HCGMxg8wC2HfN05iYhtr8coQ8Ue7gem3FT/opvbL26D+6OW 6FSsHjTT5k81/DU/oB/SojRMXiac/EXC4sXnleg8wVnSuM/qNuNWa/QRd7m1vvvDTW Rpbp64Ohpnm4g== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra210 has one XUSB device mode controller, which can be operated HS and SS modes. Add DT support for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam Reviewed-by: JC Kuo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 8fe47d6..e34a865 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -885,6 +885,23 @@ status = "disabled"; }; + xudc@700d0000 { + compatible = "nvidia,tegra210-xudc"; + reg = <0x0 0x700d0000 0x0 0x8000>, + <0x0 0x700d8000 0x0 0x1000>, + <0x0 0x700d9000 0x0 0x1000>; + interrupts = <0 44 0x4>; + power-domains = <&pd_xusbdev>, <&pd_xusbss>; + power-domain-names = "xusb_device", "xusb_ss"; + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, + <&tegra_car TEGRA210_CLK_XUSB_SS>, + <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>; + nvidia,xusb-padctl = <&padctl>; + status = "disabled"; + }; + padctl: padctl@7009f000 { compatible = "nvidia,tegra210-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>;