From patchwork Fri Sep 14 21:47:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 970132 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="AfW+Yncd"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42Bqrf60Bqz9s3l for ; Sat, 15 Sep 2018 08:27:14 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728036AbeIODnj (ORCPT ); Fri, 14 Sep 2018 23:43:39 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12324 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727065AbeIODnj (ORCPT ); Fri, 14 Sep 2018 23:43:39 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 14 Sep 2018 15:27:16 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 14 Sep 2018 15:27:13 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 14 Sep 2018 15:27:13 -0700 Received: from tbergstrom-lnx.Nvidia.com (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 14 Sep 2018 22:27:12 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 159DFF83558; Sat, 15 Sep 2018 00:47:57 +0300 (EEST) From: Peter De Schrijver To: CC: Peter De Schrijver Subject: [RFC 07/14] memory: tegra: scaled LA register for Tegra210 Date: Sat, 15 Sep 2018 00:47:48 +0300 Message-ID: <1536961675-27752-8-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1536961675-27752-1-git-send-email-pdeschrijver@nvidia.com> References: <1536961675-27752-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1536964036; bh=tp+BW8E+gUo0RbJ1HVyo2tAsoBOlPKPkjL4sp/m2l74=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type:X-Originating-IP:X-ClientProxiedBy; b=AfW+YncdoOWoc0/CV3VUsFSzdLJqMSu3D8yPohaEHjN0cE4l7iy79z13rfKmcGGK0 PqbzCqCCmmX4fkd406IcorM0wdCvoLn8zRnDQBMmov1wXnGbxlbGXMtO6fqFjNVCJ4 uR+mwD48BuJ6NawHNEC1+73ytPeCRm/gmaKCVB7xnkQnValiHN/I2iCVM0NifUKprG W4+Str208L6jn3fHcztvbF9yEo9nag7/XqQMNnKLzf4fnuMZLueBSlpo3kaC+FXmlb bg4pACfTXqDcddUEse5wX5SJd16Cz1eezPp7gDDIxmnpvySqaDCJcW1dq4u1oQ9N3V Ss4c/X+My7zQQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Signed-off-by: Peter De Schrijver --- drivers/memory/tegra/tegra210.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index aa9dcf0..b4dd533 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -53,6 +53,13 @@ #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8 #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB 0x694 +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B 0x698 +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C 0x6a0 +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB 0x69c +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB 0x6a4 +#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A 0x690 + static const unsigned long tegra210_mc_emem_regs[] = { MC_EMEM_ADR_CFG, MC_EMEM_ARB_CFG, @@ -93,6 +100,15 @@ MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7, }; +static const unsigned long tegra210_scaled_la_regs[] = { + MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB, + MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B, + MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C, + MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB, + MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB, + MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A, +}; + static const struct tegra_mc_client tegra210_mc_clients[] = { { .id = 0x00, @@ -1157,4 +1173,7 @@ .smmu = &tegra210_smmu_soc, .emem_regs = tegra210_mc_emem_regs, .num_emem_regs = ARRAY_SIZE(tegra210_mc_emem_regs), + .scaled_la_regs = tegra210_scaled_la_regs, + .num_scaled_la_regs = ARRAY_SIZE(tegra210_scaled_la_regs), + .has_scaled_la = true, };