| Message ID | 1533924845-1466-2-git-send-email-avienamo@nvidia.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | Tegra SDHCI support HS400 on Tegra210 and Tegra186 | expand |
On Fri, Aug 10, 2018 at 09:13:58PM +0300, Aapo Vienamo wrote: > Document HS400 DQS trim value device tree property. > > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> > --- > Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++++ > 1 file changed, 4 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index edecf97..32b4b4e 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -71,6 +71,7 @@ Optional properties for Tegra210 and Tegra186: trimmer value for non-tunable modes. - nvidia,default-trim : Specify the default outbound clock trimmer value. +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing Notes on the pad calibration pull up and pulldown offset values: - The property values are drive codes which are programmed into the @@ -87,6 +88,9 @@ Optional properties for Tegra210 and Tegra186: - The values are programmed to the Vendor Clock Control Register. Please refer to the reference manual of the SoC for correct values. + - The DQS trim values are only used on controllers which support + HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports + HS400. Example: sdhci@700b0000 {
Document HS400 DQS trim value device tree property. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++++ 1 file changed, 4 insertions(+)