Message ID | 1533924522-1037-33-git-send-email-avienamo@nvidia.com |
---|---|
State | Superseded |
Headers | show
Return-Path: <linux-tegra-owner@vger.kernel.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41nCqk6pxsz9rxx for <incoming@patchwork.ozlabs.org>; Sat, 11 Aug 2018 04:11:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730718AbeHJUlZ (ORCPT <rfc822;incoming@patchwork.ozlabs.org>); Fri, 10 Aug 2018 16:41:25 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:11475 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728001AbeHJUlY (ORCPT <rfc822;linux-tegra@vger.kernel.org>); Fri, 10 Aug 2018 16:41:24 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id <B5b6dd5050000>; Fri, 10 Aug 2018 11:10:13 -0700 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 10 Aug 2018 11:10:28 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 10 Aug 2018 11:10:28 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 10 Aug 2018 18:10:28 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Fri, 10 Aug 2018 18:10:27 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id <B5b6dd5110001>; Fri, 10 Aug 2018 11:10:27 -0700 From: Aapo Vienamo <avienamo@nvidia.com> To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Ulf Hansson <ulf.hansson@linaro.org>, Adrian Hunter <adrian.hunter@intel.com>, Mikko Perttunen <mperttunen@nvidia.com>, Stefan Agner <stefan@agner.ch> CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>, Aapo Vienamo <avienamo@nvidia.com> Subject: [PATCH v2 32/40] arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V Date: Fri, 10 Aug 2018 21:08:34 +0300 Message-ID: <1533924522-1037-33-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533924522-1037-1-git-send-email-avienamo@nvidia.com> References: <1533924522-1037-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: <linux-tegra.vger.kernel.org> X-Mailing-List: linux-tegra@vger.kernel.org |
Series |
Tegra SDHCI add support for HS200 and UHS signaling
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diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 212e663..8496101 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -178,16 +178,7 @@ vddio_sdmmc: ldo2 { regulator-name = "VDDIO_SDMMC"; - /* - * Technically this supply should have - * a supported range from 1.8 - 3.3 V. - * However, that would cause the SDHCI - * driver to request 2.7 V upon access - * and that in turn will cause traffic - * to be broken. Leave it at 3.3 V for - * now. - */ - regulator-min-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on;