diff mbox series

[V3,2/2] arm64: capabilities: BP harden NVIDIA Denver CPU

Message ID 1525890492-25360-2-git-send-email-dgilhooley@nvidia.com
State Deferred
Headers show
Series [V3,1/2] arm64: Add MIDR encoding for NVIDIA CPUs | expand

Commit Message

David Gilhooley May 9, 2018, 6:28 p.m. UTC 
The NVIDIA Denver CPU also requires BP hardening
so add it to the list.

Signed-off-by: David Gilhooley <dgilhooley@nvidia.com>
---
 arch/arm64/kernel/cpu_errata.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index a900bef..e4a1182 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -316,6 +316,7 @@  static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
 	MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
 	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
+	MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER),
 	{},
 };