From patchwork Thu Apr 26 14:59:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 905119 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40X0bv13kQz9ry1 for ; Fri, 27 Apr 2018 01:00:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756550AbeDZO74 (ORCPT ); Thu, 26 Apr 2018 10:59:56 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5212 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756664AbeDZO7V (ORCPT ); Thu, 26 Apr 2018 10:59:21 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 26 Apr 2018 07:59:03 -0700 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 26 Apr 2018 07:59:20 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 26 Apr 2018 07:59:20 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 26 Apr 2018 14:59:20 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Thu, 26 Apr 2018 14:59:20 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.129]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 26 Apr 2018 07:59:20 -0700 From: Jon Hunter To: Mathias Nyman , Greg Kroah-Hartman , Thierry Reding CC: , , , Jon Hunter Subject: [PATCH V2 3/3] usb: xhci: tegra: Add support for managing powergates Date: Thu, 26 Apr 2018 15:59:10 +0100 Message-ID: <1524754750-3633-3-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524754750-3633-1-git-send-email-jonathanh@nvidia.com> References: <1524754750-3633-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra XHCI controller requires that the XUSBA (for superspeed) and XUSBC (for host) power-domains are enabled. Commit 8df127456f29 ("soc/tegra: pmc: Enable XUSB partitions on boot") was added to force on these power-domains if the XHCI driver is enabled while proper power-domain support is added, to ensure the device did not hang on boot. However, rather than forcing on these power-domains in the PMC driver we can use the legacy Tegra powergate APIs to turn on these power-domains during the probe of the Tegra XHCI driver. In the near future we plan to move the Tegra XHCI driver to use the generic PM domain framework for power-domains and so to prepare for this only use the legacy Tegra powergate API if there is not PM domain associated with device (ie. dev.pm_domain is NULL). Please note that in the future the superspeed and host resets will be handled by the generic PM domain provider and so these are only these are only needed in the case where there is no generic PM domain. Signed-off-by: Jon Hunter Reviewed-by: Thierry Reding Acked-by: Thierry Reding --- Changes since V1: - None drivers/usb/host/xhci-tegra.c | 68 +++++++++++++++++++++++++++++++------------ 1 file changed, 49 insertions(+), 19 deletions(-) diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c index 85f2381883ad..862f85f4c8bb 100644 --- a/drivers/usb/host/xhci-tegra.c +++ b/drivers/usb/host/xhci-tegra.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "xhci.h" @@ -975,20 +976,6 @@ static int tegra_xusb_probe(struct platform_device *pdev) if (IS_ERR(tegra->padctl)) return PTR_ERR(tegra->padctl); - tegra->host_rst = devm_reset_control_get(&pdev->dev, "xusb_host"); - if (IS_ERR(tegra->host_rst)) { - err = PTR_ERR(tegra->host_rst); - dev_err(&pdev->dev, "failed to get xusb_host reset: %d\n", err); - goto put_padctl; - } - - tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss"); - if (IS_ERR(tegra->ss_rst)) { - err = PTR_ERR(tegra->ss_rst); - dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", err); - goto put_padctl; - } - tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host"); if (IS_ERR(tegra->host_clk)) { err = PTR_ERR(tegra->host_clk); @@ -1052,11 +1039,48 @@ static int tegra_xusb_probe(struct platform_device *pdev) goto put_padctl; } + if (!pdev->dev.pm_domain) { + tegra->host_rst = devm_reset_control_get(&pdev->dev, + "xusb_host"); + if (IS_ERR(tegra->host_rst)) { + err = PTR_ERR(tegra->host_rst); + dev_err(&pdev->dev, + "failed to get xusb_host reset: %d\n", err); + goto put_padctl; + } + + tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss"); + if (IS_ERR(tegra->ss_rst)) { + err = PTR_ERR(tegra->ss_rst); + dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", + err); + goto put_padctl; + } + + err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, + tegra->ss_clk, + tegra->ss_rst); + if (err) { + dev_err(&pdev->dev, + "failed to enable XUSBA domain: %d\n", err); + goto put_padctl; + } + + err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, + tegra->host_clk, + tegra->host_rst); + if (err) { + dev_err(&pdev->dev, + "failed to enable XUSBC domain: %d\n", err); + goto disable_xusba; + } + } + tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies, sizeof(*tegra->supplies), GFP_KERNEL); if (!tegra->supplies) { err = -ENOMEM; - goto put_padctl; + goto disable_xusbc; } for (i = 0; i < tegra->soc->num_supplies; i++) @@ -1066,7 +1090,7 @@ static int tegra_xusb_probe(struct platform_device *pdev) tegra->supplies); if (err) { dev_err(&pdev->dev, "failed to get regulators: %d\n", err); - goto put_padctl; + goto disable_xusbc; } for (i = 0; i < tegra->soc->num_types; i++) @@ -1076,7 +1100,7 @@ static int tegra_xusb_probe(struct platform_device *pdev) sizeof(*tegra->phys), GFP_KERNEL); if (!tegra->phys) { err = -ENOMEM; - goto put_padctl; + goto disable_xusbc; } for (i = 0, k = 0; i < tegra->soc->num_types; i++) { @@ -1092,7 +1116,7 @@ static int tegra_xusb_probe(struct platform_device *pdev) "failed to get PHY %s: %ld\n", prop, PTR_ERR(phy)); err = PTR_ERR(phy); - goto put_padctl; + goto disable_xusbc; } tegra->phys[k++] = phy; @@ -1103,7 +1127,7 @@ static int tegra_xusb_probe(struct platform_device *pdev) dev_name(&pdev->dev)); if (!tegra->hcd) { err = -ENOMEM; - goto put_padctl; + goto disable_xusbc; } /* @@ -1199,6 +1223,12 @@ static int tegra_xusb_probe(struct platform_device *pdev) disable_rpm: pm_runtime_disable(&pdev->dev); usb_put_hcd(tegra->hcd); +disable_xusbc: + if (!&pdev->dev.pm_domain) + tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); +disable_xusba: + if (!&pdev->dev.pm_domain) + tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); put_padctl: tegra_xusb_padctl_put(tegra->padctl); return err;