From patchwork Fri Dec 8 08:58:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 846041 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ytR9B3kvbz9s82 for ; Fri, 8 Dec 2017 19:58:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752713AbdLHI6x (ORCPT ); Fri, 8 Dec 2017 03:58:53 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17392 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752303AbdLHI6w (ORCPT ); Fri, 8 Dec 2017 03:58:52 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 08 Dec 2017 00:58:41 -0800 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 08 Dec 2017 00:59:36 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 08 Dec 2017 00:59:36 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 8 Dec 2017 08:58:51 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 8 Dec 2017 08:58:51 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 08 Dec 2017 00:58:51 -0800 From: Manikanta Maddireddy To: , , , CC: , , , , , , , , , , , Manikanta Maddireddy Subject: [PATCH V4 3/7] PCI: tegra: Remove PCI_REASSIGN_ALL_BUS flag for Tegra PCIe Date: Fri, 8 Dec 2017 14:28:09 +0530 Message-ID: <1512723493-865-4-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1512723493-865-1-git-send-email-mmaddireddy@nvidia.com> References: <1512723493-865-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Primary, secondary and subordinate default bus numbers are 0 in Tegra and it is expecting SW to program these numbers in configration space. pci_scan_bridge_extend() function programs these numbers in configuration space if secondary & subordinate bus numbers are 0 or PCI_REASSIGN_ALL_BUS flag is set. Since secondary & subordinate default bus numbers are 0, PCI_REASSIGN_ALL_BUS flag can be removed for Tegra PCIe. Signed-off-by: Manikanta Maddireddy Acked-by: Thierry Reding --- V3: * new patch in V3 V4: * no change in this patch drivers/pci/host/pci-tegra.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index a549c5899e26..0d91f1a3a6b4 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -2604,7 +2604,6 @@ static int tegra_pcie_probe(struct platform_device *pdev) tegra_pcie_enable_ports(pcie); - pci_add_flags(PCI_REASSIGN_ALL_BUS); host->busnr = pcie->busn.start; host->dev.parent = &pdev->dev; host->ops = &tegra_pcie_ops;